Nippon Electric Co., Ltd.

Nec Corporation

Akira Nagami

An improved semiconductor memory which can achieve high-speed data processing is disclosed. The memory comprises a memory array, a random access port for accessing a desired one of memory cell in accordance with row and column addresses, a serial read circuit for consecutively reading data from the selected row one by one and a serial write circuit for consecutively writing data to the selected row one by one without specific column address information.

Semiconductor memory device having serial writing scheme

An improved semiconductor memory, suitable for a video system, includes a memory cell array, a first access circuit operatively performing a write operation and a read operation to the memory cell array, and a second access circuit operatively performing a read operation to the memory cell array in response to different groups of address signals from those applied to the first access circuit. The two access circuits can operate asynchronously and can simultaneously access the memory.

Semiconductor memory having multiple access

A dynamic memory is capable of performing an internal charge storing refreshing operation with a low power consumption. The memory comprises an inverter for receiving a signal from the outside. The inverter is composed of an input transistor and a load circuit whose ability to feed a current to the input transistor is controllable and is made smaller during the internal refresh operation.

Dynamic random-access memory

A memory circuit capable of detecting that refresh operation is surely ended is disclosed. The memory circuit comprises a memory cell matrix, a dummy array sharing rows with the memory cell matrix and similar column structure to the memory cell matrix, and means coupled to a pair of digit lines of the dummy array for detecting that a potential at either of the pair of digit lines in the dummy array reaches an amplified low level.

Memory circuit

A latch circuit has first to fourth nodes. The first node is supplied with a logic signal and the second node is charged at a first potential. A potential at the third node is discharged to the second potential. The fourth node is charged to the first potential. This all happens during a first period, after which, and during a second period, a potential at the second node is transferred to the third node. An inverter transistor is responsive to a level of the logic signal at the first node for discharging a potential of the second node to a second potential when the logic signal level is in the first potential and for retaining the first potential of the second node when the logic signal level is in the second potential. A transfer between the fourth and the first nodes is responsive to the second potential at the third node for discharging the potential of the fourth node to the second potential. A true and a complement signals of a large amplitude are established at the fourth and second nodes.

High speed latch circuit

An output buffer circuit operable at a high-speed and stably holding output level is disclosed. The output buffer circuit comprises a pair of input transistors receivivable a true and a complementary signals, a pair of output nodes from which amplified signals of the true and complementary signals are derived, a pair of switching gates coupled between the drains of the input transistors and the output nodes and control means for operatively disenabling the switching gates when logic state of the true and complementary signals applied to the input transistors is reversed.

Output circuit

An improved dynamic-type digital circuit provided with a level refresh means for refreshing a logic signal retained at a high impedance is disclosed. The circuit comprises a signal node, a control node, a voltage source, switching means coupled between the signal node and the voltage source, the switching means being controlled by a level of the control node, control means responsive to a level of the signal node for determining a level at the control node, capacitor means coupled to the control node at its one end and means for supplying the other end of the capacitor means with a control signal.

Semiconductor circuit

A two-clock multi-address input dynamic random access memory provided with an internal refresh function for refreshing memory cells without receiving refresh address information from the outside is disclosed. The memory characteristically comprises a terminal for receiving a refresh control signal, refresh address means for designating a row address to be refreshed, means for producing confirmation signal when a reset precharge of a circuit relating to a refresh operation is completed, means for storing the refresh control signal when a row address strobe signal is in active level, and means responsive to the confirmation signal and the stored refresh signal for effecting the refresh operation.

Memory device

The invention provides for maintaining a charged node point at the potential level of a power source, when the potential must be dynamically sustained. This is done by a circuit using insulated-gate, field-effect transistors. Preferably, two such transistors are used in conjunction with a bootstrap capacitor which changes the potential of a signal appearing at a circuit node responsive to any leaking of current at an output, which might otherwise cause the node potential to drift down to a lower level.

Circuit using insulated-gate field-effect transistors

In a dynamic random access memory including means for inputting a row strobe signal and means for inputting a column strobe signal, and having the functions of incorporating a row address input in response to the row strobe signal and incorporating a column address input in response to the column strobe signal, an improvement comprising a first insulated gate field effect transistor having its drain coupled to a first junction point, its gate receiving the column strobe signal and its source supplied with a first power supply, means for charging the first junction point within a period of active level of the row strobe signal, a second insulated gate field effect transistor having its drain coupled to the first junction point, its gate coupled to a second junction point and its source supplied with the first power supply terminal, means for precharging the second junction point within a period of absence of the row strobe signal, and a third insulated gate field effect transistor having its drain coupled to the second junction point, its gate supplied with the column strobe signal and its source supplied with the first power supply. After completion of a desired operation with respect to a selected memory cell, the row strobe signal is placed at its inactive level to be reset while the column strobe signal is at its active level. Then, after a necessary reset period when the row strobe signal is made active, a change from inactive level to active level of the first junction point is suppressed to thereby inhibit active operation based on the column strobe signal.

Flexible hidden refresh memory circuit

An amplifier circuit for amplifying an input signal and obtaining true and complementary output signals includes cross-coupled transistors connected to first and second nodes. The first and second nodes are made to be an equal potential by precharging. Then, the potential of the first node is either maintained or changed to a lower (in absolute value) level in response to and dependently on a control input signal, while the potential of the second node is slightly lowered (in absolute value) by dividing the precharged change of the second node with a capacitor. Thus, the first node is controlled by the input signal, while the second node is given a reference potential determined by a capacitance division ratio.

Amplifier circuit for obtaining true and complementary output signals

A timing signal generator includes a field-effect transistor having a drain supplied with a command signal and a source connected to an output node. The gate of the transistor is connected to a circuit node which is precharged to a voltage to render the transistor conductive prior to the activation of the command signal. A delay circuit having a predetermined delay time has an input connected to the output node and an output connected to a circuit for discharging the output node and the circuit node in response to the output of the delay circuit.

Growing community of inventors

Tokyo, Japan

Akira Nagami