Kyocera Corporation

Akira Murao

Norihiko Matsushima

Junji Aranami

Norikazu Ito

Jumpei Sato

Akihiro Mizumoto

Kenji Kusuhara

The solar cell element includes a semiconductor substrate with first and second surfaces, a passivation layer being in contact with the second surface, a protective layer located on the passivation layer, a bus bar electrode, and a collecting electrode. The bus bar electrode is in contact with the second surface in a first gap portion penetrating the passivation layer and the protective layer, and is sandwiching a gap region with the passivation layer and the protective layer in a first direction along the second surface. The collecting electrode includes an electrode layer located on the protective layer, a first connecting portion located in the gap region and connecting the electrode layer and the second surface, and a second connecting portion penetrating the passivation layer and the protective layer and connecting the electrode layer and the second surface in a second gap, and is electrically connected with the bus bar electrode.

Solar cell element

A solar cell element is provided with a semiconductor substrate, a passivation layer, and an electrode. The semiconductor substrate has a first surface and a second surface that is positioned on a back side of the first surface. The passivation layer is positioned on the second surface of the semiconductor substrate. The electrode is positioned on the passivation layer and positioned in the state of being electrically connected to the semiconductor substrate. The electrode includes a linear electrode part that is positioned along a peripheral edge of the semiconductor substrate when the semiconductor substrate is seen from the second surface side in plane perspective view, and is positioned in the state of penetrating the passivation layer in a thickness direction.

Solar cell element and method for manufacturing solar cell element

The solar cell element includes a semiconductor substrate with first and second surfaces, a passivation layer located on the second surface, a protective layer located on the passivation layer, and a back-surface electrode located on the protective layer. The back-surface electrode is electrically connected to the semiconductor substrate via one or more hole portions penetrating the protective layer and the passivation layer. The protective layer includes a first region showing a tendency to increase in thickness as a distance from an inner edge portion of the hole portion and a second region surrounding the first region. A distance between a position of the first region farthest from the inner edge portion and the inner edge portion is larger than a thickness in the second region. The back-surface electrode shows a tendency to decrease in thickness on the first region as a distance from the inner edge portion.

Growing community of inventors

Moriyama, Japan

Akira Murao