Matsushita Electric Industrial Co., Ltd.

Godo Printing Ink Mfg. Co., Ltd.

Osaka Municipal Technical Research Insititute

Akira Miyoshi

Takashi Taniguchi

Nobuo Higaki

Keizo Sumida

Toru Morikawa

Hiroaki Yamamoto

Masaya Sumita

Yoshito Nishimichi

Tokuzo Kiyohara

Tamotsu Nishiyama

Hideshi Nishida

Kozo Kimura

Shinji Ozaki

Hiroshi Kadota

Hiroyuki Morishita

Yasuyuki Agari

Shirou Yoshioka

Yoshiaki Kasuga

Satoshi Takashima

Satoshi Ogura

Seiji Tokunoh

Atsushi Ito

Ryohei Tsuboi

Yuiti Hashimoto

The present invention provides a transparent heat radiating coating composition capable of forming a coating layer having excellent transparency and heat radiating properties. The transparent heat radiating coating composition of the present invention is a transparent heat radiating coating composition including a binder resin, a hydrotalcite-series compound and a resin dispersant with an amine value of 0 to 90 mgKOH/g, wherein the transparent heat radiating coating composition includes 50 to 290 parts by weight of the hydrotalcite-series compound based on 100 parts by weight of the binder resin.

Transparent heat radiating coating composition

Each of D flip-flops (FFs)toconstituting a scan path circuit has a normal operation input circuit to be selected in a normal operation and a test operation input circuit to be selected in a test operation, and a control signal having an intermediate voltage between a supply voltage and a ground voltage is sent from a voltage generating circuitto the test operation input circuit of each FF in the test operation. In this case, the amount of an output change in data in each FF is smoother than that in the case in which the supply voltage is applied. Consequently, the delay time of the data is increased. The intermediate voltage to be applied to each FF in the test operation is determined based on a feedback signal sent from a test circuitfor checking whether scanned-out data have an error or not.

Scan path circuit and semiconductor integrated circuit comprising the scan path circuit

A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit has a selector for simultaneously performing a plurality of data transfers which are each made from a register file of one processing element to an operation unit of another processing element. With the provision of this selector that can perform such simultaneous data transfers, the processing efficiency of the processing elements can be maintained even if a change occurs in operand assignments and the like.

Data processor and program for processing a data matrix

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST D' is decoded, the sum-product result registeroutputs its held value to the path P. The comparatorcompares the magnitude of the held value of the sum-product result registerwith the coded 32-bit integer '0x0000_00FF'. The polarity judging unitjudges whether the eighth bit of the value held by the sum-product result registeris &#x201c;ON&#x201d;. The multiplexeroutputs one of the maximum value &#x201c;0x0000_00FF&#x201d; generated by the constant generator, the zero value &#x201c;0x0000_0000&#x201d; generated by the zero generator, and the held value of the sum-product result registerto the data bus

Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing

Adder circuit and associated layout structure

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction &ldquo;MCSST D,&rdquo; is decoded, the sum-product result register,outputs its held value to the path P,The comparator,compares the magnitude of the held value of the sum-product result register,with the coded 32-bit integer &ldquo;0x0000_00FF&rdquo;. The polarity judging unit,judges whether the eighth bit of the value held by the sum-product result register,is &ldquo;ON&rdquo;. The multiplexer,outputs one of the maximum value &ldquo;0x0000_00FF&rdquo; generated by the constant generator,the zero value &ldquo;0x0000_0000&rdquo; generated by the zero generator,and the held value of the sum-product result register,to the data bus

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST D1' is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer '0x0000.sub.-- 00FF'. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is 'ON'. The multiplexer 24 outputs one of the maximum value '0x0000.sub.-- 00FF' generated by the constant generator 21, the zero value '0x0000.sub.-- 0000' generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

Processor which can favorably execute a rounding process composed of

In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.

Method and apparatus for automatically designing logic circuit, and

A semiconductor integrated circuit includes a functional block realizing at least part of a function of the semiconductor integrated circuit. The functional block includes a plurality of basic cells and a plurality of terminal cells. Each of the plurality of terminal cells has a connector for mediating a communication between another semiconductor integrated circuit and one of the plurality of basic cells.

Semiconductor integrated circuit and system incorporating the same

A partial product adder for summing up four partial products P0, P1, P2, and P3 which are binary numbers in twos-complement representation having different weights is composed of a carry save adder consisting of an array of 4:2 compressors each having four inputs. Of the four inputs of each 4:2 compressor, the input W presents the shortest propagation delay, while the inputs Y and Z compose critical paths. To implement sign extension of the first partial product P0 having the smallest weight, a logic circuit provides, in a plurality of digit positions higher than the sign digit P0s of the first partial product, values resulting from a logic operation between the value of the sign digit P0s of the first partial product and the value of the sign digit P1s of the second partial product having the second smallest weight. The first partial product P0 after sign extension is allocated to the input W of the carry save adder, while the plurality of upper digits of the input Z related to the second partial product P1 have their values fixed to 0. This reduces a time penalty accompanying the sign extension.

Arithmetic processing apparatus

A mantissa X.sub.Mk, which satisfies 1.ltoreq.X.sub.Mk &lt;2, is fed to a mantissa process section in order that the iterative multiplication operation of normalized floating-point numbers X.sub.k (k=0, . . . , m), written P=X.sub.0 .times.X.sub.1 .times.X.sub.2 .times.0 . . . .times.X.sub.m, is performed. In the mantissa process section, a product represented in RB (redundant binary) number representation is stored in a register, and such a product is fed back to a multiplier without being converted into a binary number. A shifter for one-place right-shift is provided between the multiplier and the register. A converter sequentially converts each RB number stored in the register into a binary number and provides to the shifter a shift-amount signal S.sub.1 whose value varies with the result of such RB-to-binary number conversion. If a digit that is positioned upward two places from the binary point of a binary number obtained by the conversion is 0, then the value of S.sub.1 is set to 0. If such a digit is 1, then the value of S.sub.1 is set to 1.

Iterative arithmetic processor

A signal cache memory controller which includes line for inputting an index section of an address is formed with a branch line which is intervened by an address delay circuit. In each of banks X and Y, a switching circuit selects the data which has been delayed in response to a select signal Sse being outputted as a cache-access address to be outputted to a tag memory. An address comparator compares a tag section of the address input through a signal line for inputting the tag section with a reference address output from the tag memory and outputs an coincidence signal if there is a coincidence therebetween. When the coincidence signal is generated and the select signal Sse is not generated, a bank-hit signal generating circuit generated a bank-hit signal Sbh, in response to which a select-signal generating circuit generates the select signal Sse. The circuit for controlling a cache memory which is divided into a plurality of banks enables the writing of data in the cache in every cycle.

Control circuit for controlling a cache memory divided into a plurality

A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.1 according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.

Small-sized, low power consumption multiplication processing device with

A multiplication processing device provided with a recoding circuit for dividing an M-digit number (M is a natural number), the radix of which is .UPSILON., into consecutive N-digit sets (N is a natural number equal to or less than M) and for calculating an intermediate sum S.sub.i and an intermediate carry C.sub.i according to Z.sub.gi =C.sub.i .times..UPSILON..sup.N +S.sub.i (Z.sub.gi is the value of an ith set (i represents natural numbers equal to or greater than a predetermined number)) and for adding the intermediate sum S.sub.i corresponding to the ith set to an intermediate carry C.sub.i-1 corresponding to an (i-1)th set for each value of i and a selection circuit for selecting one of one or more numbers having the same format as that of the intermediate carry C.sub.i corresponding to the ith set and for outputting the selected number to the recoding circuit as the intermediate carry C.sub.i-1 corresponding to the (i-1)th set.

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Osaka, Japan

Akira Miyoshi