Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Akira Masuo

Norihiko Sumitani

Yasuhiro Agata

Tsuyoshi Koike

Shigeo Houmura

Kenji Sugihara

Yoshinobu Yamagami

Hidenari Kanehara

Junichi Yukawa

Kazuki Tsujimura

Noriaki Narumi

Yuichirou Ikeda

An acquisition unit acquires at least one of first information and second information. A notification unit provides warning information to the driver, the warning information being generated based on at least one of the first information and the second information acquired and indicating a possibility of an increase in an insurance premium of an insurance applied to the driver. An reception unit receives acceptance of the provided warning information from the driver. A processor determines to transmit the acceptance by the driver of the possibility of an increase in the insurance premium to an insurance company server when the acceptance is received and determines to transmit at least one of the first information and the second information to the insurance company server when acceptance is not received.

Driver assistance device that can be mounted on a vehicle

A system LSI () having a logic circuit () and a plurality of SRAM macros () includes a power supply circuit () configured to receive a voltage (VDDP) supplied from the outside of the system LSI (), and to generate a stabilized voltage (VDDM) lower than the voltage (VDDP). An SRAM memory cell () of each of the plurality of SRAM macros () is supplied with the voltage (VDDM) generated by the power supply circuit (), and an SRAM logic circuit () of each of the plurality of SRAM macros () is supplied with a voltage (VDD) supplied from the outside. In addition, the logic circuit () is supplied with the voltage (VDD) from the outside.

Semiconductor integrated circuit

A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which control the first transistors. The drain or source of each first transistor is connected to an input of the corresponding first logic gate, and the gate of each first transistor is connected to an output of the corresponding first logic gate. The first transistors are driven by pulses.

Semiconductor memory device

A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width.

A precharge circuit steps up a voltage of a bit line connected to a memory cell to a power supply voltage. A plurality of step-down circuits step down the voltage of the bit line to a voltage level lower than the power supply voltage before data is read from the memory cell. The plurality of step-down circuits are connected to the bit line, and the plurality of step-down circuits are controlled by step-down control signals different to each other.

Semiconductor storage device

In a memory cell having a first and a second load transistor, a first and a second drive transistor, and a first and a second access transistor, a third access transistor provided between a first bit line and a first memory node and having a gate terminal connected to a first column line and a fourth access transistor provided between a second bit line and a second memory node and having a gate terminal connected to a second column line, are additionally provided.

The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node.

Decoder circuit

A storage node voltage control circuit is added to a memory cell including two load transistors, two drive transistors and two access transistors. The storage node voltage control circuit performs control so that in writing data into the memory cell, a voltage at one of the two storage nodes holding a low logic level is raised without changing voltages at respective sources of the load transistors.

The semiconductor integrated circuit includes: a first transistor of a first conductivity type connected between a first power supply and an output node and turned ON according to a first clock to put the output node to a first logic level; a second transistor of a second conductivity type turned ON according to an input signal; a third transistor of the second conductivity type connected in series to the second transistor and turned ON according to a second clock; and a fourth transistor of the first conductivity type connected between the first power supply and the output node and turned ON according to a feedback signal. The second and third transistors are connected between the output node and a second power supply. The fourth transistor is turned from ON to OFF after both the second and third transistors are turned ON.

Growing community of inventors

Osaka, Japan

Akira Masuo