Hitachi, Ltd.

Okayama University

Akira Masaki

Minoru Yamada

Keiichirou Nakanishi

Hiroyuki Itoh

Michio Asano

Toshio Yamada

Noboru Masuda

Masayoshi Yagyu

Kenichi Ishibashi

Masakazu Yamamoto

Mitsuo Usami

Takehisa Hayashi

Tohru Kobayashi

Kuninori Imai

Nobuo Tamba

Ryotaro Kamikawai

Kazuo Sato

Akio Takahashi

Takahiro Daikoku

Akira Yamagiwa

Hiroki Yamashita

Motoyo Wajima

Tomoyuki Hamada

Fumiyuki Kobayashi

Ichiro Nakamura

Yutaka Harada

Kohji Kamejima

Masakazu Ejiri

Mitsugu Kusunoki

Toshio Doi

Katuo Sugawara

Takashi Nishida

Masato Hamamoto

Hirotoshi Tanaka

Mitsuo Asai

Masami Yamasaki

Moritoshi Yasunaga

Masahide Tokuda

Kichie Matsuzaki

Katuaki Chiba

Makoto Kuwata

Ryuichi Satomura

Mitsuru Usui

Satoshi Hososaka

Masayoshi Yagyuu

Yuzo Hirai

Mararu Osanai

Motohisa Funahashi

Junichi Nishihashi

Takeshi Miyazaki

Hiroyuki Itho

Masaru Osani

Masaru Osanai

Yohei Matsumoto

An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes. The present invention solves problems by proposing a design method for an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit and a semiconductor integrated circuit including an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit.

Integrated circuit with multidimensional switch topology

A variable logic circuit comprises a memory cell, a transistor which turns on or off depending on data stored in the memory cell, a transistor which is connected in series to the above-mentioned transistor and is turned on or off by an input signal, a transistor which produces a voltage depending on the conduction states of the above-mentioned transistors, and transfer means which conducts or does not conduct the produced voltage to the output terminal depending on a select signal.

Variable logic circuit and semiconductor integrated circuit using the

A programmable two-line, two-phase logic array has a plurality of inputs, each having two input signals operating in two phases and memory cells provided at an intersection of the input signal lines and output lines corresponding to at least one function that cross the input lines. The memory cells are capable of being written in the fabrication process or by a field programming process that addresses the contact points at which the input and output lines cross. The two-line, two-phase logic circuit can be attained by the same technique as that used for attaining a conventional PLA without designing circuitry based on a conventional synchronous logic beforehand followed by replacing it with a two-line, two-phase circuit.

Programmable two-line, two-phase logic array

A resource recycling system and a product circulation system, wherein a search is made for information regarding specifications and production methods for a recovered product and an original product is produced with the recovered product used as resources. These systems include a plurality of production factories for producing a predetermined products, and housing a production apparatus and a reclamation factory. A communication network is connected for transmitting therebetween production information necessary for producing products. Also a recycle plate is created for identifying a production apparatus. The plate is used to transmit accounting information on an amount of money required to reproduce the product from the reclaimed resources. The reclamation apparatus also identifies a production apparatus by which a recovered product was produced, extracts production information on the recovered product and generates a disassembly procedure for the recovered product from the extracted production information.

Systems and methods for recycling resources and circulating products

A semiconductor integrated circuit device has, in one embodiment, a pair of signal transmission lines formed over and insulated from a semiconductor substrate, a first circuit formed in the semiconductor substrate and electrically connected with one end of the pair of signal transmission lines for sending an electric signal, and a second circuit formed in the semiconductor substrate and electrically connected with the other end of the pair of signal transmission lines for receiving the electric signal propagating over the transmission line pair. A control resistance is electrically connected between the pair of transmission lines at the above-mentioned other end for controlling a delay time of the signal propagating over the pair of signal transmission lines between the opposite ends of the pair of signal transmission lines.

Semiconductor integrated circuit device having a signal transmission

An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

Information processing system

A switching circuit which comprises a digital circuit formed of a superconductor, a transmission line connected to the digital circuit through magnetic coupling, and a resistor element disposed in the transmission line for differentiating the output of the digital circuit.

Switching circuit and its signal transmission method

A transistor circuit of this invention comprises a first transistor for receiving a first bias at its base, resistor means connected to the collector of the first transistor and clamp means connected to the junction between the first transistor and the resistor means, and obtains an output from a terminal of the resistor on the opposite to its junction with the first transistor. When a noise current due to .alpha. rays develops in the first transistor and the output is lowered, the clamp means operates in such a manner that the current flows through the clamp means and prevents the change of the output. The transistor circuit of this invention is connected to a resistor or a transistor and operates as a constant current circuit for supplying a current to the resistor or the transistor so that the current flowing therethrough becomes constant. For example, it is used as a constant current source of an emitter follower to constitute a level shift circuit. It is disposed in a feedback part and used as a constant current source in a logic circuit comprising a logic part consisting of a differential transistor circuit and the feedback part for negatively feeding back the in-phase output of the differential transistor circuit.

Transistor circuit with improved .alpha. ray resistant properties

An integrated circuit is disclosed in which a plurality of semiconductor substrates are stacked in such a manner that an insulating board, provided with (1) structure, such as grooves, for transmitting a coolant so as to dissipate heat, and (2) an electrical interconnection member for electrically connecting adjacent semiconductor substrates, is sandwiched between semiconductor substrates. In order to attain the high-speed signal transmission between a semiconductor substrate and an insulating board, a signal current flows not only in a main surface of the semiconductor substrate but also in directions perpendicular to the main surface. The insulating board may be formed of an insulating silicon carbide plate which has a plurality of grooves filled with a metal.

High density integration of semiconductor circuit

An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to .alpha. rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as .alpha. rays and does not cause soft errors.

Flip-flop circuit

A semiconductor device includes a plurality of circuit groups constituting an integrated circuit and each constituted by a plurality of circuit blocks and a bias circuit which applies a bias potential to said circuit blocks. The device further includes a plurality of power buses provided above the circuit groups through an insulating layer so as to feed power to circuit elements in the circuit groups. At least one of the power buses is constituted by a first bus for feeding power to the circuit groups and a plurality of second buses respectively provided for the circuit groups so that each second bus receives power from the first bus and feeds power to circuit elements in the corresponding circuit group. Each of the second buses is connected to the first bus at a predetermined position on the corresponding circuit group.

Lead arrangement for reducing voltage variation

A logic circuit including an input transistor receiving the input signal at its emitter, an output transistor in emitter-follower configuration receiving the signal from the collector of the input transistor, a voltage dividing resistor pair connected to the collector of the input transistor, and a feedback circuit conducting the signal produced by the voltage dividing resistor pair back to the base of the input transistor, the output signal being produced at the emitter of the output transistor.

Input buffer circuit and logic circuit using the buffer circuit

A laminated multilayer electric circuit is comprised of wafers having each internal electric circuits and laminated one after another. A signal transfer circuit used in the laminated multilayer electric circuit for transfer of signals between the wafers through an electrostatic capacitor has a receiving circuit of sufficiently high input resistance for receiving a signal from a capacitance electrode forming the electrostatic capacitor, and a circuit for clamping the level of the signal substantially within the input amplitude for the receiving circuit. The signal transfer circuit permits the signal transfer to be performed not through a flip-flop or the like and consequently at high speeds.

Signal transfer circuit for use in laminated multilayer electric circuit

An output circuit comprises an output transistor circuit for applying an output signal to a transmission line connected to an output terminal, a circuit for driving the output transistor circuit in response to an input signal applied to an input terminal, and a control circuit by which the signal amplitude of a first wave applicable to the transmission line with a load connected to the output terminal through the transmission line is rendered approximately one half of the output signal amplitude with a load directly connected to the output terminal. The control circuit includes a monitoring transistor within the same chip as the output transistor circuit, a selected one of the output resistance and input signal of the output transistor circuit being controlled in accordance with the magnitude of the drain current of the monitoring transistor to adjust the amplitude of the signal applied to the transmission line. Transmission with transmitting and receiving ends having a well-defined transmission waveform is obtained, thereby making possible high-speed signal transmission between LSI chips.

Output circuit having transistor monitor for matching output impedance

A multilayer wiring board structure includes a plurality of conductor layers and insulation layers interleaved between each ones of the conductor layers. The conductor layers includes power (or ground) line layers and signal line layers, and one type of insulation layer having lower relative permittivity and another type of insulation layer having higher relative permittivity is used between power (ground) line layers interposed by signal line layer(s).

Hybrid multilayer wiring board

Growing community of inventors

Musashino, Japan

Akira Masaki