Fujitsu Corporation

Oji Paper Co., Ltd.

Fujitsu Vlsi Limited

Akira Kobayashi

Shinji Saito

Kenji Yasuda

Makiko Tokita

Masahiro Nakagawa

Masahiko Kitajima

Hisao Maruyama

Masao Maekawa

A PLL circuit of the pulse swallow-type prescaler system prevents erroneous module count operations such as are caused by a delay in the module signal, without the need to use a device which operates at high speeds or a device of large power. In a synthesizer of the pulse swallow-type prescaler system, a PLL circuit has a PLL COUNTER circuit and a module pulse generating circuit and a prescaler circuit has a prescaler counter, an extender circuit and a module control circuit which outputs a module control signal MO, for controlling the module operation, upon sensing the logic state of the module pulse generating signal MK, which is output by the module pulse signal generating circuit in response to the output signal MD of the PLL counter circuit.

PLL circuit of pulse swallow-type prescaler system

This invention aims at providing a PLL synthesizer circuit that can shorten lock-up time while sufficiently securing a time constant of a low-pass filter, and has a structure wherein a phase comparator 3 outputs output signals .phi.R and .phi.P on the basis of a reference signal fr output from a reference frequency divider 2, and a comparison signal fp output from a comparison frequency divider 4; the output signals .phi.R and .phi.P are negatively fed back to the comparison frequency divider 4 through a charge pump 5, a low-pass filter 6 and a voltage controlled oscillator 7, and a lock detection circuit 8 outputs a lock signal LD when in a locked state. When an output signal SVCO of the voltage control oscillator 7 coincides with a set frequency, when the lock detection circuit 8 does not output the lock signal LD, a reset circuit 15 outputs a reset signal PC to the reference frequency divider 2 and to the comparison frequency divider 4, and the reset signal PC brings the phase of the reference signal fr into conformity with the phase of the comparison signal fp.

PLL synthesizer having frequency dividers with reset control

A PLL synthesizer circuit includes a reference frequency generator for generating a reference frequency signal and a reference clock signal, a phase comparator for comparing a phase of the reference frequency signal with an output signal and for outputting a phase difference signal having a pulse form, and a voltage-controlled oscillation device for generating the output signal having a frequency dependent on the phase difference signal. The PLL synthesizer circuit also includes a phase lock detecting circuit for determining whether or not the phase difference signal has a pulse width in which the reference clock signal successively changes n times (n is numeral equal to or greater than 2) and for outputting a phase lock detection signal representing that the PLL synthesizer circuit is in a phase-locked state when it is determined that the reference clock signal does not successively change n times in the pulse width of the phase difference signal. There is also provided a pulse width detecting circuit suitable for application of a phase lock/unlock detection in a PLL synthesizer.

Pulse width detecting circuit and PLL synthesizer circuit using the same

A PLL synthesizer circuit includes a lowpass filter including capacitors for restricting an output voltage of the lowpass filter, a charge pump circuit for controlling the output voltage of the lowpass filter by charging or discharging the capacitors of the lowpass filter, a voltage controlled oscillator for outputting an output signal having a frequency which is controlled by the output voltage of the lowpass filter, a frequency divider for frequency-dividing the output signal of the voltage controlled oscillator to output a comparison signal and having a variable frequency dividing ratio, a phase comparator for comparing a phase of a reference signal having a predetermined frequency and a phase of the comparison signal output from the frequency divider to output phase error information which indicates a phase lead and a phase lag of the comparison signal with respect to the reference signal, and a charge pump control circuit for forming control information based on the phase error information when switching a frequency of the output signal of the voltage controlled oscillator from a first frequency to a second frequency and for supplying the control information to the charge pump circuit. The charge pump circuit charges or discharges the capacitors of the lowpass filter independently of the reference signal based on the control information until the output signal of the voltage controlled oscillator reaches the second frequency, so as to raise or lower the output voltage of the lowpass filter depending on the charging or discharging. The output signal of the voltage controlled oscillator is used as an output signal of the PLL synthesizer circuit.

PLL synthesizer circuit

An ink-jet recording sheet that contains as main ingredients 69-95% wood pulp and 4-30 wt % precipitated calcium carbonate and which has a Stockigt sizing degree of 2-25 seconds as measured for a basis weight of 64 g/m.sup.2, or a Stockigt sizing degree ranging from 5.times.(basis weight/64).sup.2 to 25.times.(basis weight/64).sup.2 at a water extracting pH of 4.5-7.5. This sheet allows a clear color to develop and provides an image having circular dots and sharply defined edges. This sheet may also incorporate a cationic synthetic polymer and an alkylketene dimer.

Ink-jet recording sheet

An ink jet recording sheet having an enhanced ink-absorbing property and bright color image-forming property and an excellent surface hardness has a specific coating layer formed on a surface of a substrate sheet, which comprises a pigment and a resinous binder composed of a cationic copolymer prepared by copolymerizing (a) 99.95 molar % or less of a principal copolymerization component comprising at least one fatty acid vinyl ester comonomer with (b) 0.05 to 0.4 molar % of a cationic copolymerization component comprising at least one cationic comonomer having an ethylenically unsaturated hydrocarbon radical and a cationic radical selected from tertiary amino radicals and quaternary ammonium radicals and, optionally, a member selected from (c) an additional copolymerization component comprising at least one polymerizable non-ionic comonomer different from the fatty acid vinyl ester and (d) a graft copolymerization component comprising polyvinyl alcohol.

Ink jet recording sheet and process for producing same

An ink jet recording sheet includes a sheet-like substrate composed mainly of 70 to 100 wt % of wood pulp and 0 to 30 wt % of precipitated calcium carbonate and having a Stockigt sizing degree of not less than 2 seconds and not more than 25 seconds when formed into a sheet having a basis weight of 64 g/m.sup.2, and a coating layer composed mainly of white pigment, with the coating layer being formed on at least one side of the substrate at a weight of 1 to 10 g/m.sup.2. This sheet has a high ink absorption rate and is able to develop bright colors and sharp images.

Growing community of inventors

Kasugai, Japan

Akira Kobayashi