Fujitsu Corporation

Kabushiki Kaisha Toshiba

Other

Fujitsu Semiconductor Limited

Akira Kikutake

Kuninori Kawabata

Satoshi Eto

Masato Matsumiya

Yasuhiro Onishi

Shinichiro Shiratake

Toshikazu Nakamura

Toru Koga

Toshimi Ikeda

Yuichi Uzawa

Atsushi Takeuchi

Atsushi Hatakeyama

Yuki Ishii

Nobutaka Taniguchi

Masato Takita

Ayako Kitamoto

Kota Hara

Hideki Kanou

Masatomo Hasegawa

Toshiya Miyo

Shigemasa Ito

Junichi Sasaki

Shuzo Otsuka

Masato Matsuyima

In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.

Semiconductor memory device

Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, and thus writes test data into a regular memory cell at a location corresponding to a location of a parity memory cell into which test parity data are written in each of regular cell arrays. Therefore, since a common test pattern can be used to test both the regular memory cell and the parity memory cell, test cost can be curtailed.

Semiconductor memory

Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data according to read data that are simultaneously read from the first and second regular cell arrays. A main parity generation circuit generates according to sub parity data parity data in common to the regular cell arrays, is not disposed in a distributed manner but disposed corresponding to the parity cell array. Thus, the layout design, layout verification, and so forth of a semiconductor memory can be prevented from being complexed. As a result, the parity generation circuit can be optimally laid out, decreasing the development time and defect analysis time for the semiconductor memory can be decreased.

Semiconductor memory having sub-party cell array error correction

During a first data compression test mode which disables an error correction function, first test data are written to a first regular memory block. Second test data are written to not only a second regular memory block, but a parity memory block. By changing the number of bits distributed to the first and second test data (compression rate of data), a data compression test for a parity memory block can be performed without need to increase the number of test terminals. As a result, the test time can be decreased and the test cost can be decreased.

Semiconductor memory having error correction

A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.

Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit

A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.

Semiconductor integrated circuit device

A semiconductor memory device having a shift redundancy function includes a switch circuit for changeably connecting a plurality of decode signal lines decoding an address signal to a plurality of selecting lines and redundancy selecting lines, and executes a switch operation for shifting at least one of a plurality of decode lines in the direction of a first redundancy selecting line positioned at one of the ends among a plurality of selecting lines or a second switch operation for shifting at least one of the decode lines in the direction of a second redundancy selecting line positioned at the other end among the selecting lines or both of the first and second operations when any fault occurs in a plurality of selecting lines. The semiconductor memory device preferably includes two or more first redundancy selecting lines positioned at one of the ends of a plurality of selecting lines, two or more second redundancy selecting lines positioned at the other end, and first and second switch units disposed in two stages. When any fault selecting line occurs, the first switch unit executes a first switch operation for shifting at least one of the decode signal lines in the direction of the first redundancy selecting line or a second switch operation for shifting the same in the direction of the second redundancy selecting line, or the second switch unit executes a third switch operation for shifting at least one decode signal line in the direction of the first redundancy selecting line or a fourth switch operation for shifting it in the direction of the second redundancy selecting line.

Semiconductor memory device and method for executing shift redundancy operation

An internal address generating circuit sequentially generates internal addresses in the burst read operation, with an external address being set as an initial value. A memory core has plural memory cells and sequentially outputs, in response to activation of a column selection signal, data read from the memory cells corresponding to the internal addresses in the burst read operation. In the burst read operation, a column control circuit in a memory core control circuit repeats activation of the column selection signal for a certain period during an activation period of an external control signal and forcibly deactivates the column selection signal in synchronization with deactivation of the external control signal. In the burst read operation, an operation state control circuit in the memory core control circuit deactivates an operation state control signal after a predetermined time has elapsed from the deactivation of the external control signal.

A semiconductor memory device includes a plurality of first fuse latch circuits configured to provide redundancy to first addresses, a plurality of second fuse latch circuits configured to provide redundancy to second addresses, and a nullifying circuit configured to make the plurality of second fuse latch circuits ineffective, wherein first fuse positions corresponding to the plurality of first fuse latch circuits intervene between second fuse positions corresponding to the plurality of second fuse latch circuits.

Semiconductor memory device with reliable fuse circuit

Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.

Semiconductor memory having an error correction function

A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (), a load circuit (), and an amplifier circuit (). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.

Memory device

A semiconductor device includes input circuits which capture respective data pieces from an exterior of the device in synchronization with respective clock signals supplied from the exterior of the device, a pulse signal generation circuit which generates a pulse signal, and drive circuits which supplies the respective data pieces captured by the input circuits to internal circuitry at a unified timing corresponding to the pulse signal.

Semiconductor device having simplified internal data transfer

The present invention is a memory circuit which selects N number of segments out of M number of segments (N<M) during normal reading, wherein all the M number of segments are activated during a read test in order to drive a common data bus for testing by a plurality of sense buffers in the M number of segments. For this, test signals are supplied to a column decoder, and segment select signals, for activating the M number of segments, are generated in response to the test signal. In this way, a plurality of segments in a memory bank in a select status can be simultaneously selected to execute a read test, and the efficiency of a compression read test can be improved.

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Kawasaki, Japan

Akira Kikutake