Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Akira Kawabe

Gorou Mori

Kouji Okamoto

Shinichi Ogita

Akio Yokoyama

Akira Yamamoto

Shiro Sakiyama

Takashi Morie

Hitoshi Kobayashi

Takayasu Kito

Hideki Nishino

Fumiaki Senoue

Koichi Nagano

Kiyotaka Tanimoto

A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Voltage measuring apparatus

A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time &#x394;&#x3a3; A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time &#x394;&#x3a3; A/D converters to feed back the digital signal to the digital filter.

Actuator driver

In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion () based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (). A test can be performed by supplying a test signal in place of the input analog signal. A control portion () performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal. A test signal can be input with a small-scale configuration, without providing a test signal line separately from a line used for normal operation.

Pipeline A/D converter

Multiple stages sequentially convert respective input analog signals to partial digital data. Each stage includes: a partial A/D converter; a partial D/A converter; an adder that adds/subtracts the analog signal from the previous stage and an output from the partial D/A converter; and a gain amplifier that amplifies an output of the adder and supplies to the next stage. The pipelined A/D converter further includes: a correction value adding unit that adds a correction value to the output from the decoder unit; a correction value calculating unit that, based on the output from the correction value adding unit, calculates an error between the median of the output data and an ideal median at two points in the stage input/output characteristics, saves the calculated value as the correction value and supplies it to the correction value adding unit; and a control unit that controls the above units so as to perform the correction operation. Thereby, aliasing at decoding of the stage output is prevented, enabling an output range to be used effectively.

Pipelined A/D converter

In a playback signal processing device for extracting, from an analog playback signal, playback data and a clock synchronized with the playback data, a digital equalizeris disposed outside a clock extraction loop formed by an interpolator, a timing recovery circuit, and a control circuit. The digital equalizeris provided between an A/D converterand the interpolatorand performs equalization processing on digital playback data from the A/D converterin accordance with the timing of a fixed clock CLK from a synthesizer. The coefficients of the digital equalizerare updated by the control circuitby using a coefficient setting deviceaccording to frequency ratio informationfrom the timing recovery circuit. Accordingly, the clock extraction capability is enhanced in spite of the equalization processing on the playback signal by the digital equalizer.

Playback signal processing device

A digital analog converter includes a current conversion section and a voltage conversion section. The current conversion section has a first output terminal and a second output terminal. The first output terminal outputs a first current and a second output terminal outputs a second current, the first current varying in value according to inputted digital data, the sum of the first current and the second current becoming a constant current. The voltage conversion section converts the first current to a corresponding first voltage and produces an offset voltage on the basis of the constant current and outputs the sum of the first voltage and the offset voltage as an output voltage.

Current addition type digital analog converter

In a phase error detecting circuit used in a synchronous clock extracting circuit for extracting a clock which is synchronized with reproduced data, a cross reference value generatorinputs, as a rising cross reference value S, rising phase error data Scalculated in a phase error calculatorto a rising cross detectorand inputs, as a falling cross reference value S, falling phase error data Ssimilarly calculated to a falling cross detector. Each of the cross detectorsandcalculates a difference value between the value of the reproduced data at a sampling point and the inputted cross reference value (cross offset value) Sor Sand outputs a rising or falling cross detection signal when one of two difference values at consecutive sampling points is negative and the other thereof is positive. Accordingly, a capture range is enlarged.

Phase error detecting circuit and synchronization clock extraction circuit

An unusual waveform detection circuit is a digital-type unusual waveform detection circuit that arbitrarily sets a threshold used for determining an unusual waveform and produces an unusual waveform determination signal by comparing an input signal with the threshold. In producing the unusual waveform determination signal, one of a configuration where a voltage at each of all sampling points is compared with a reference voltage and a configuration where a continuously changing gradient of signal waveform peaks is calculated and is compared with a reference gradient is selectively employed. The unusual waveform detection circuit can easily and accurately detect various unusual waveforms.

Information playback apparatus with an unusual waveform circuit

In a state where a PLL circuit is not locked, a gain control signal according to the difference between a peak value of a reproduced signal and the upper or lower limit value of the dynamic range of an A/D converter is given to a variable gain amplifier. In a state where the PLL circuit is locked, a gain control signal according to the difference between the reproduced signal and a reference value that corresponds to a level to which the reproduced signal belongs is given to the variable gain amplifier for each sampling point of the A/D converter. The variable gain amplifier amplifies the reproduced signal with a gain according to the gain control signal.

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Osaka, Japan

Akira Kawabe