Texas Instruments Corporation

Akira Karashima

Mutsumi Masumoto

Kenji Masumoto

Norito Umehara

Masazumi Amagai

Margaret Simmons-Matthews

Sohichi Kadoguchi

Chikara Azuma

A semiconductor device comprising a semiconductor chip having an active and a passive surface, the passive surface adhesively attached to a substrate film by means of a multilayer composite; this composite comprising a metal foil having first and second surfaces and an adhesive layer attached on each of these surfaces. The multilayer composite has an average modulus larger than the modulus of the encapsulating molding compound used in the semiconductor device. By applying the composite to assembling face-up chip-scale devices, stress in solder joints is reduced and solder fatigue life enhanced.

Semiconductor package with metal foil attachment film

In semiconductor device under this invention, bonding pads are lined up in a staggered pattern on the main surface of semiconductor chip which is mounted on insulated substrate . Multiple stud bumps are stacked on top of the pads which are located on the inner rows, and these stud bumps comprise stud bump stack . Conductive wire connects the lands on the insulated substrate with the corresponding bonding pads . The wire is formed with its beginning at the land and its end at the bonding pad. Via the stud bump stacks , the ends of conductive wire on the inner pads are in a higher position than the ends of conductive wires on the outer pads, so that the problem of neighboring conductive wires coming into contact does not occur.

Method of manufacturing a semiconductor chip comprising multiple bonding pads in staggard rows on edges

A semiconductor package according to the present invention includes a die attachment area for receiving a die attachment material and a stitch bond area for receiving a wire lead from a die. The stitch bond area is adjacent to said die attachment area on the substrate. Moreover, a stud bump is formed on the substrate for preventing the die attachment material from contacting the stitch bond area when a die is attached to the die attachment area. A method for manufacturing a semiconductor package according to the present invention also is disclosed.

Semiconductor packages and methods for manufacturing such semiconductor packages

In semiconductor device under this invention, bonding pads are lined up in a staggered pattern on the main surface of semiconductor chip which is mounted on insulated substrate Multiple stud bumps are stacked on top of the pads which are located on the inner rows, and these stud bumps comprise stud bump stack Conductive wire connects the lands on the insulated substrate with the corresponding bonding pads The wire is formed with its beginning at the land and its end at the bonding pad. Via the stud bump stacks the ends of conductive wire on the inner pads are in a higher position than the ends of conductive wires on the outer pads, so that the problem of neighboring conductive wires coming into contact does not occur.

Semiconductor device and its manufacturing method

The purpose of the present invention is to reduce the warpage of the semiconductor package caused by thermal contraction. According to the present invention, semiconductor device (,) has plate-shaped member (,) which is positioned on a surface of semiconductor chip (,) and is sealed together with semiconductor chip (,) with molding resin (,). Said plate-shaped member (,) has a linear expansion coefficient that is less than the linear expansion coefficient of the aforementioned molding resin. By placing a plate-shaped member with a small linear expansion coefficient on semiconductor chip (,), it is possible to reduce the thermal contraction on the upper side of the semiconductor chip. Also, the presence of the plate-shaped member on the semiconductor chip leads to substantial reduction in the thickness of the molding resin on the semiconductor chip. The pulling force due to contraction of the molding resin that leads to warping is proportional to the thickness of the molding resin. Consequently, by using semiconductor device (,) of the present invention that contains the aforementioned plate-shaped member, it is possible to reduce the warpage of the package to a very low level.

Semiconductor device

In semiconductor device fabrication, warping of the support pins must be prevented so that the semiconductor element can be properly positioned during the wire-bonding and resin-sealing processes. The invention provides a process in which a V-shaped groove 33, for example, is formed in the mounting pad 31 and the support pins 32, imparting rigidity to the support pins 32.

Rigidized lead frame for a semiconductor device

A lead frame composed of an outer frame and inner lead frame portions formed as an integral frame wherein each lead frame portion directly joins the outer frame at some of the four corners of the lead frame portion with circuitous bridges interposed for fixation of the lead frame portion to the outer frame at each of the other corners.

Growing community of inventors

Oita, Japan

Akira Karashima