Nec Corporation

Nippon Electric Co., Ltd.

Akira Kanemasa

Akihiko Sugiyama

Fujio Nakagawa

Kunihiko Niwa

Shinichi Aikoh

Hisashi Sakaguchi

An echo canceller includes a first transversal filter for generating a first echo canceling signal to be canceled from an output signal from a sampler, the first echo canceling signal corresponding to a first sampling value of an echo response waveform of an echo path by a sampling clock when no sampling clock jitter occurs, a second transversal filter for generating a second echo canceling signal corresponding to a difference between the first sampling value and a second sampling value when the sampling clock jitter occurs, two subtractors for canceling the first and second echo canceling signals from a digital reception signal output from the sampler, and a controller for detecting the sampling clock jitter and performing a control operation such that a tap coefficient value of the second filter is added to a tap coefficient value of the first filter to update the tap coefficient value of the first filter, and thereafter, the second echo canceling signal generating operation of the second filter is disabled.

Echo canceller

An echo canceller of this invention cancels an echo signal input to a sampler through an echo path upon 2-wire/4-wire conversion. The echo canceller includes a filter having a characteristic for reducing a tail of an echo response waveform and inserted between an output terminal of the sampler and a reception output terminal, a first transversal filter for generating a first canceling signal for canceling an echo signal sampled at equal sampling clock intervals after the echo signal passes through the filter, a second transversal filter for canceling a deviation of a sampling value obtained when sampling clock is jittered before the deviation passes through the filter, an enable/disable unit for enabling/disabling a tap output of the second transversal filter, and a controller for, from a moment at which the sampling clock is jittered, controlling the enable/disable unit to cancel a deviation in correspondence with a deviation value of an actual sampling value.

In a time division multiplexing method or device wherein first through N-th-channel samples are extracted at first through M-th unit intervals which correspond to first through M-th bit rates of first through N-th-channel input signals, where M is equal to or less than N, a control signal is produced in response to the input signals to indicate first through M-th consecutive fields in each of successive frames of a time division multiplexed signal and to indicate whether the samples are significant or insignificant samples in each frame. The first through the M-th fields correspond to the unit intervals and have a predetermined total time duration in each frame. The control signal is used moreover to arrange the samples in the fields of each frame by selecting the significant samples with preference to the insignificant samples. Together with the control signal, a sample arrangement information signal is produced to indicate arrangement of the samples in each frame and is arranged in an information field which remains in each frame. Depending on the number of the samples arranged in each field with the unit interval corresponding to the field under consideration, time durations of the fields may vary from frame to frame.

Time division multiplexing method with channel compression and a device

A first difference signal is obtained by subtracting an echo replica from a mixed signal which consists of a received signal and an echo. The echo replica is produced in an adaptive digital filter using an error signal. The first difference signal includes the received signal and a residual echo, and is delayed in a manner to produce a delayed first difference signal. The delayed first difference signal is subtracted from the first difference signal to obtain a second difference signal. Thereafter, a polarity of the residual echo included in said second difference signal is detected. The error signal is obtained based on the detected polarity, and then is applied to the adaptive digital filter.

Method of cancelling echoes in full-duplex data transmission system

An improved decision feedback equalizer, which removes intersymbol interference from pulse transmissions having a desired period, includes an arithmetic circuit (9) for extracting a residual intersymbol interference signal from a residual signal and a delayed residual signal which is produced by delaying the residual signal. The residual signal is produced by a subtractor circuit (2) which subtracts an estimated intersymbol interference signal from the pulse transmissions. A pattern detector circuit (11) is also provided to detect a particular consecutive pattern from a demodulated data sequence produced by a decision or detection circuit (3) for demodulating the residual signal. The residual intersymbol interference signal and a reference signal are inputted to a selector (10) responsive to the output of the pattern detector circuit. The output of the selector is sent to an adaptive filter circuit (50) which also receives the demodulated data sequence produced by the detection circuit and outputs the estimated intersymbol interference signal. The decision feedback equalizer can be modified to provide additional adaptive filter circuits for estimating intrasymbol interference, such that both intersymbol and intrasymbol interference signals can be removed from the pulse transmissions.

Decision feedback equalizer with a pattern detector

A method and apparatus cancels an echo by using an echo replica generated such that a tap coefficient of an adaptive filter is sequentially updated, the echo being received from a transmitting end to a four-wire side through a two/four wire converter and being obtained such that a pulse signal having positive and negative polarities is fed into a receiving end, wherein a difference signal (error signal) between the echo replica and a reception signal is calculated; a correlation value between a signal representing a polarity of the error signal and a signal representing a polarity of the echo replica is calculated; when the correlation value is smaller than a predetermined value, a first of two types of tap coefficients which belong to each of a plurality of taps is updated based on at least the error signal and is set as the tap coefficient of the adaptive filter during a period in which the pulse signal is set in the positive polarity, and a second type of tap coefficient is updated based on at least the error signal and is set as the tap coefficient of the adaptive filter during a period in which the pulse signal is set in the negative polarity; and when the correlation value is larger than the predetermined value, the first and second types of tap coefficients are updated irrespective of the polarity of the transmission pulse on the basis of the error signal.

Method and apparatus for cancelling echo

An echo canceller for cancelling echoes which result from impedance mismatching in a two-wire/four-wire conversion circuit. The prior art employed an input terminal, an output terminal, a transmitter section, a receiver section, a digital-to-analog converter, an adaptive digital filter, a subtractor, a sample hold circuit, an analog-to-digital converter, a multiplier, a low pass filter, a hybrid circuit, and a two-wire communication path, for the purpose of generating a replica of the echo signal to cancel such echos. A method has also been proposed which employs a polarity discriminator circuit instead of an analog-to-digital converter, and utilizes approximation algorithms to correct an adaptive digital filter tap coefficient using the signs of an error signal. In order to carry out this alternative method, the invention employs a fast convergence system comprising a circuit for generating an echo replica in response to a transmit signal, a circuit for producing a difference signal by subtracting the echo replica from a signal which contains a receiver signal and echo, a circuit for multiplying and averaging the difference signal and a polarity of the echo replica, a circuit for absorbing a fluctuation in an absolute value of the averaged output, and a circuit for adaptively varying a tap correction amount of a filter of the echo canceller in response to an output of the fluctuation absorbing circuit.

Fast convergence method and system for echo canceller

An echo canceler performs convergence in a multiple step manner using a plurality of adaptive digital filters. The adaptive digital filters are sequentially operated to supply data to the corresponding D/A converters such that the echo signals are sequentially cancelled in a stepwise manner. Random access memories are used to allow a decrease in the required number of bits and thus the dimensions of the memories, hence in the overall circuit, so that a compact LSI echo canceler can be easily obtained.

Echo canceler with cascaded filter structure

A digital signal processor is disclosed suited for LSI fabrication comprising a data input circuit for carrying out scaling on a plurality of serial data supplied through a first external terminal group; a coefficient input circuit for carrying out 2's complement conversion on a plurality of specific data from a plurality of serial data supplied through a second external terminal group; a multiplier circuit for carrying out a plurality of multiplications and additions on data from the data input and coefficient input circuits; and an adder circuit for carrying out a plurality of additions and subtractions as well as overflow detection and correction. Data connections in each of the circuits are altered depending on a combination of logical zeros and ones entered through a fourth external terminal group so that one of a plurality of functional modes is selected.

Digital signal processor suited for LSI fabrication

In a recursive digital filter for dealing with data words given by two's complement representation in a common word format comprising a sign bit, an integer bit, and a predetermined number of fractional bits, an overflow detect and correct circuit is supplied with simultaneously produced sign bits of bit-serial first sum, feedback, and second sum data words and with the integer bit of the second sum data word and detects overflow in the second sum data word to produce, for use in the circuit, an overflow detect pulse indicative of presence or absence of overflow. In either event, the circuit produces an overflow-free data word for use in the filter. When overflow is detected, the circuit produces a polarity decision pulse that decides polarities of the overflow-free bits. Otherwise, the circuit determines the overflow-free bits directly by the corresponding bits of the second sum data word. Use is preferred of a first and a second timing signal which specify time slots for the sign bit and a prescribed bit, respectively, of each serial data words and which are for directly deciding the overflow-free fractional bits by the polarity decision pulse and for producing a second polarity decision pulse for direct decision of polarities of the overflow-free sign and integer bits. A memory having a plurality of memory areas is preferred for production of the overflow detect and the polarity decision pulses and of the overflow-free bits.

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Tokyo, Japan

Akira Kanemasa