Harris Corporation

Intersil Corporation

Intersil Americas Inc.

Akira Ito

Michael D Church

John T Gasner

Kantilal Bacrania

Choong-Sun Rhee

Jeffrey Michael Johnston

Glenn A Dejong

Gregory J Scott

Glenn Alan DeJong

Gregory J Fisher

Glenn A DeJong

Dave Kutchmarick

Jeffrey M Johnston

An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P&plus; buried layers,and,on opposite sides of N&plus; buried layer,. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.

Analog-to-digital converter and method of fabrication

An integrated circuit with a passive component and an ESD device in accordance with the present invention has: a P substrate; an N+ buried layer implanted in the P substrate; a cathode coupled to the N+ buried layer with an N area formed between the cathode and the N+ buried layer; an anode coupled to the N+ buried layer with a P area formed between the anode and the N+ buried layer; and a first P+ buried layer implanted in the N+ buried layer and below the P area to form a Zener diode. In an alternative embodiment, the ESD device may be incorporated in an integrated circuit with an active component.

Method for fabricating electrostatic discharge protection device

An integrated circuit has a pseudosubstrate 6060 with an isolation moat 9505. Substrate 6001 has one conductivity and a subcircuit region 6060 has an opposite conductivity. Digital CMOS devices are formed in the subcircuit over region 6060 and operate between zero to +5 volts. Analog devices are formed over the rest of the substrate and operate between plus and minus 5 volts. The moat 9505 isolates the digital CMOS devices from the analog devices.

Electrostatic discharge protection device

A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concentrations are both optimized by adjustment of the two variables N base implant dose and P base implant dose; this determines the NPN base carrier concentration which turns out to provide good NPN characteristics. Low voltage NMOS source and drain implants employ a higher dose and may also be used for the high voltage NMOS source. The NPN emitter doping may also be used for a contact to the high voltage NMOS drain contact.

BiCMOS devices

Method of fabricating BiCMOS devices

The double lightly diffused transistor has drain regions with a lightly doped arsenic region 42 entirely contained within a lightly doped phosphorus region 40. The arsenic region is implanted with a dose less than 1.times.10.sup.15 ions/cm.sup.2 and is preferably implanted with a dose of about 3.times.10.sup.3 to 2.times.10.sup.14 ions/cm.sup.2. The drains are silicided for ohmic contact.

Double diffused MOS device and method

A semiconductor device which includes a polysilicon gate separated from a semiconductor substrate by a re-oxidized nitrided oxide film in which the concentration of re-oxidized nitride in the film underlying the gate is non-uniform and in which the concentration of nitrogen in the substrate and the re-oxidized nitrided oxide along their interface and underlying the gate is non-uniform. Methods are disclosed of providing the non-uniform concentrations by incomplete shielding of the oxide by the gate during the nitriding and re-oxidizing process.

Non-uniformly nitrided gate oxide and method

A method of making a semiconductor device in which a polysilicon gate is separated from a semiconductor substrate by a re-oxidized nitrided oxide film and in which the concentration of re-oxidized nitride in the film underlying the gate is non-uniform. The concentration of nitrogen in the substrate and the re-oxidized nitrided oxide along their interface and underlying the gate is non-uniform. The non-uniform concentrations are provided by incomplete shielding of the oxide by the gate during the nitriding and re-oxidizing processes.

Method of making non-uniformly nitrided gate oxide

A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Analog-to-digital converter

An ESD protection diode for a CMOS or BiCMOS integrated circuit formed by imbedding a Zener diode in the drain of a MOS device used as a protection diode. The Zener diode may be formed with the preexisting process steps of a BiCMOS process, and it provides a low voltage trigger for avalanche breakdown in the MOS ESD protection diode.

Electrostatic discharge protection

A bipolar transistor having an improved collector structure includes a buried region of the same conductivity type as the collector region spaced from the base region and having a laterally graded impurity concentration with the lowest below the center of the emitter .region. An integrated circuit may include transistors having the buried collector region of the diminishing lateral impurity concentration below the center of its emitter as well as having transistors with a uniform lateral impurity concentration below the total lateral extent of the emitter. A method of achieving the unique collector region includes forming at least a first collector region of a first conductivity type as two lateral portions of substantially uniform lateral impurity concentration with a space therebetween in a substrate of a second conductivity type and heating to form the buried collector structure of diminishing lateral impurity concentration. This is followed by forming a collector layer on the substrate, forming a base region in the collector region and an emitter region in the base region over the space in the buried collector region. If the integrated circuit includes transistors which do not have the unique graded collector, the buried collector region for these transistors is formed by introducing impurities having substantially uniform lateral impurity concentration in the substrate.

Method of making an improved graded collector for inductive loads

A bipolar transistor having an improved collector structure includes a buried region of the same conductivity type as the collector region spaced from the base region and having a laterally graded impurity concentration with the lowest below the center of the emitter region. An integrated circuit may include transistors having the buried collector region of the diminishing lateral impurity concentration below the center of its emitter as well as having transistors with a uniform lateral impurity concentration below the total lateral extent of the emitter. A method of achieving the unique collector region includes forming at least a first collector region of a first conductivity type as two lateral portions of substantially uniform lateral impurity concentration with a space therebetween in a substrate of a second conductivity type and heating to form the buried collector struture of diminishing lateral impurity concentration. This is followed by forming a collector layer on the substrate, forming a base region in the collector region and an emitter region in the base region over the space in the buried collector region. If the integrated circuit includes transistors which do not have the unique graded collector, the buried collector region for these transistors is formed by introducing impurities having substantially uniform lateral impurity concentration in the substrate.

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Palm Bay, FL, United States of America

Akira Ito