Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Broadcom Corpotation

Avago Technologies General IP Pte, Ltd.

Akira Ito

Shom Ponoth

Henry Chen

Xiangdong Chen

Qing Liu

Agnes Woo

Wei Xia

Qintao Zhang

Changyok Park

Guang-Jye Shiau

Todd Lee Brooks

Myron Buer

Douglas D Smith

Liming Tsau

Henry Kuo-Shun Chen

Khim Leng Low

Vincent Chen

Surya Battacharya

Jay Shiau

Chao-Yang Lu

Arya Behzad

Joseph H King

Jung Wang

Jiong Zhang

Pascal Tran

Mei Xue

Kenneth Yau

Wenwei Yang

Joseph King

Henry Kuoshun Chen

A transistor structure includes a substrate and a fin structure on the substrate. The fin structure includes an undoped portion, a first doped portion, and a second doped portion. The transistor structure includes an electrode on the fin structure between the first doped portion and the second doped portion, and an insulating layer on the fin structure. The transistor structure includes a first trench in the insulating layer at a first side of the fin structure and between the electrode and the second doped portion, and a second trench in the insulating layer at a second side of the fin structure and between the electrode and the second doped portion. The first trench includes a first conductive material, and the second trench includes a second conductive material.

Transistor structures

A capacitor includes a shallow trench isolation (STI) layer disposed on top of a substrate. The capacitor also includes a first dielectric layer disposed on top of the STI layer. The capacitor further includes a metallization diffusion (MD) layer disposed within both of the STI layer and the first dielectric layer.

Ultra high density metal-oxide-metal capacitor

A finFET LDMOS semiconductor device includes a first well disposed adjacent to a second well on a substrate and a third well disposed on the substrate, wherein the second well is disposed between the first well and the third well. Additionally, the finFET LDMOS semiconductor device includes a source disposed on the first well, a fin at least partially disposed on the first well and adjacent to the source, a drain disposed on the third well, a shallow trench isolation (STI) disposed at least partially in the third well, and a STI protection structure disposed on the substrate between the second well and the third well and along a side of the STI that is closest to the source, wherein the STI protection structure is configured to discourage a drain to source current from flowing along the side of the STI that is closest to the source.

FinFET LDMOS devices with improved reliability

A fin-shaped field-effect transistor device is provided. The fin-shaped field effect transistor device may include a semiconductor substrate having a top and a bottom surface. The fin-shaped field effect transistor device may also include a fin structure disposed on the top surface of the semiconductor substrate, where the fin structure includes a first sidewall and a second sidewall opposite of the first sidewall. The first sidewall is adjacent to a first region of the top surface of the semiconductor substrate and the second sidewall is adjacent to a second region of the top surface of the semiconductor substrate. The fin-shaped field effect transistor device may also include an insulation layer disposed above the fin structure and the first and second regions of the top surface. The fin-shaped field effect transistor device may also include a conductor structure disposed above and adjacent to the insulation layer.

Fin-shaped field effect transistor and capacitor structures

A semiconductor device includes a substrate having a first well region comprising a first dopant and a second well region comprising a second dopant. The semiconductor device includes semiconductor fin structures formed on the substrate, where at least one semiconductor fin structure has a channel region along a channel axis through the first well region. The semiconductor device includes a drain region and a source region formed on the semiconductor fin structures. The first well region and the drain region are formed to operate at a first operating voltage, and the second well region and the source region are formed to operate at a second operating voltage that is smaller than the first operating voltage. The semiconductor device includes a gate structure and a dummy gate disposed on respective portions of the semiconductor fin structures, where the dummy gate is disposed between the gate structure and the drain region.

FinFET cascode laterally-diffused semiconductor device

Laterally diffused MOSFETs on fully depleted SOI are provided. A laterally diffused MOSFET includes a substrate and a first semiconductor layer disposed on the substrate. The laterally diffused MOSFET also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer that comprises a first gate region, a drain region, and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source and drain regions. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. A second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation. A gate node is coupled to the first and second gate regions to apply a gate voltage to the first and second gate regions.

Laterally diffused MOSFET on fully depleted SOI having low on-resistance

A FinFET semiconductor device having semiconductor body including a source region of a first type, and a drain region of a second type, and a drain-region shallow trench isolation (STI) disposed in the drain region. The device includes a plurality of fins attached to the semiconductor body and extending across the semiconductor body, a channel gate disposed over a section of the plurality of fins; a supplemental gate disposed on the drain-region STI.

FinFET LDMOS devices with additional dynamic control

A semiconductor device having a first stack and a second stack of device components. The first stack has a transistor switching element having a channel, a source in contact with the channel, a drain in contact with the channel, and a gate structure at least partially disposed in a space defined between and separating the source and the drain. The first stack has a source connection to the source, and a drain connection to the drain. The second stack of device components is disposed underneath the first stack and has a semiconductor substrate of a doping type the same as the drain, and a pair of electrical contacts spaced apart on the semiconductor substrate and contacting a conduction path in the semiconductor substrate extending between the pair of electrical contacts. The drain connection is connected to one of the pair of electrical contacts.

Three dimensional LVDMOS transistor structures

Semiconductor devices are provided that use both silicon on insulator region and bulk region of a fully depleted silicon on insulator (FDSOI) device. For example, a semiconductor device includes a drain region that is disposed above a first type well and a first drain extension region that is disposed above the first type well and laterally spaced apart from the drain region. The semiconductor device further includes a second drain extension region that is disposed above the first type well and is laterally spaced apart from the drain region and the first drain extension region. The semiconductor device further includes a source region disposed above a second type well and laterally spaced apart from the second drain extension.

FDSOI LDMOS semiconductor device

An Ultra Thin Body and Box (UTBB) fully depleted silicon on insulator (FDSOI) field effect transistor (FET) employing a split gate topology is provided. A gate dielectric layer is disposed beneath a gate structure and in contact with a channel layer of the device. The gate dielectric layer contains two portions, a thin portion and a thick portion. The thin portion is arranged and configured to reduce a trans-conductance of the device, while a thick portion is arranged and configured to increase the break down voltage of the device. The device further contains a bulk region that can be electrically connected to voltage source to provide control over the threshold voltage of the device.

UTBB FDSOI split gate devices

A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a semiconductor layer. The semiconductor layer includes a first doped source/drain region, a second doped source/drain region and a region comprising germanium. The program gate is disposed above the region comprising germanium and includes a first gate dielectric layer disposed below a gate conductor. The word line gate is disposed between the first doped source/drain region and the second doped source/drain region.

Method of making a fully depleted semiconductor-on-insulator programmable cell and structure thereof

A field effect transistor (FET) with raised source/drain region of the device so as to constrain the epitaxial growth of the drain region. The arrangement of the spacer layer is created by depositing a photoresist over the extended drain layer during a photolithographic process.

Extended drain MOS device for FDSOI devices

A field effect transistor (FET) having one or more fins provides an extended current path as compared to conventional finFETs. A source terminal is disposed on a first fin between a first dummy gate and a gate structure. A drain terminal is disposed on a second fin between a second dummy gate and a third dummy gate. A first gate oxide layer disposed under second and third dummy gates is made to be thinner than a second gate oxide layer disposed under the first dummy gate and the gate structure. By making the first gate oxide layer thinner, an overall footprint of the finFET device is reduced.

Reduced footprint LDMOS structure for finFET technologies

A one-time programmable memory (OTP) is provided that includes a combined word line programming line (WL-PL). The OTP includes a programmable transistor having a first threshold voltage and a first breakdown voltage, and a pass transistor having a second threshold voltage and a second breakdown voltage. The combined WL-PL is electrically connected to respective gate electrodes of both the programmable transistor and the pass transistor so that both receive the same control voltage. The second gate electrode has a work function that is greater than that of the first gate electrode, so that the second gate breakdown voltage is greater than the first gate breakdown voltage, which enables the use of the combined WL-PL.

Growing community of inventors

Irvine, CA, United States of America

Akira Ito