Sony Corporation

Akira Iga

Toshitada Doi

Tomoya Yamaura

Shinichi Kuroda

Kentaro Odaka

Katsuyuki Tanaka

Shigeru Arisawa

Susumu Kusakabe

Tadashi Ezaki

Hideo Nakamura

Nobuyuki Yasuda

Osamu Hamada

Katsumi Okayama

Yuichiro Hamada

Jyoji Hukuda

An authentication device that the user wears reads biometrics information and executes individual authentication by verification. Only when the individual authentication has been successfully performed, authentication with an external unit (such as a server) can be started. Then, only when both the individual authentication based on the biometrics information and the mutual authentication between the external unit (such as a server) and the authentication device have been successfully performed, subsequent data processing, such as payment processing, can be executed. Therefore, even if a fraudulent third party uses a stolen authentication device, because the party cannot satisfy the start condition of authentication with the external server or a PC, fraudulent transactions and other illegitimate behaviors are effectively prevented.

Authentication processing system, authentication processing method, authentication device, and computer program

Disclosed is a flat-type antenna apparatus which has a radiating conductor and a reference conductor disposed opposite to each other and performs feeding between the radiating conductor and the reference conductor at a position offset from the center of the radiating conductor center. The antenna includes: an insulative material layer which has relative magnetic permeability greater than 1 and is placed in a gap between the radiating conductor and the reference conductor; and a short-circuiting conductor which is disposed at a position to suppress unintended excitation and enables electric conduction between the radiating conductor and the reference conductor.

Antenna apparatus

Method and apparatus for providing communication with a higher communication rate while maintaining the occupied frequency band narrow, a signal processing unit of a reader/writer unit Biphase Shift Keying (BPSK)-modulates data to be transmitted, and thereafter outputs the modulated signal to a modem. The modem Amplitude Shift Keying (ASK)-modulates the modulated signal and outputs the ASK-modulated signal to a first loop coil. The first loop coil generates a magnetic field corresponding to the modulated wave. An IC card converts a part of the magnetic field radiated from the reader/writer unit with another loop coil to generate a power source from the electrical signal, and also extracts the data transmitted. In the case of transmitting the data to the reader/writer unit, a load of another loop coil is changed in accordance with the data. The reader/writer unit detects, with the first loop coil, any change in load of another loop coil of the IC card magnetically coupled with the first loop coil.

Data processing apparatus and method and data transmitting/receiving

A method for transmitting time-sharing multidata in which data series of a plurality of channels are time-sharing multiplexed to form a transmitting data series having the steps of adding error detecting or error correcting redundant bits and synchronizing redundant bits to predetermined number of information bits contained in the respective data series of the channels to form one transmitting unit, forming bit groups in a manner as to take each bit corresponding to each other between the channels as one group with respect to the information bits, the error detecting or error correcting redundant bits and the synchronizing redundant bits of said one transmitting unit of each of the channels, time-sharing multiplexing the data series so as to form one frame in which these bit groups are sequentially continued to each other and using the synchronizing redundant bits as a frame synchronizing signal of the transmitting data series.

Method for transmitting time-sharing multidata

In a digital signal transmission system, a predetermined number of words of digital information signals are added bit by bit in a modulo 2 adder to produce a first parity signal. The information signals and the first parity signal are delayed so as to have different delay times to each other, and the signals thus delayed are again added bit by bit in a modulo-2 adder to produce a second parity signal. The predetermined number of words of information signals and first and second parity signals are serially transmitted through a transmission line.

Burst-error correcting system

Blocks of digital words containing an error correcting word are time interleaved into time-interleaved blocks of words, each of which contains no more than one word from any one of the original blocks. The time-interleaved blocks of words are converted to a bit-by-bit serial digital data stream which is time-base compressed to permit insertion therein of an error detecting code word and synchronizing signals. The resulting serial data stream may be recorded on a VTR. After reproduction, each time interleaved block is checked for errors and is then time de-interleaved to reconstruct the original blocks of digital words. If one or more errors exist in words in a time-interleaved block, no more than a single word in any one of the time de-interleaved blocks contains an error. Single-word errors in a reconstructed block are corrected using the error correcting word accompanying the reconstructed block.

Error correcting system

A fluid flow control system has a fluid source and plural flow pipes connected to the fluid source. Each of the pipes has an opening of a specific area corresponding to one of the bit orders of a PCM (Pulse Code Modulated) input signal. The flow-condition of the fluid through each of the pipes is controlled by the PCM signal without changing the PCM signal to an analog signal. The summation of the outflow from each of the pipes combines to produce an analog flow output signal in response to the PCM input signal.

Fluid flow control speaker system

In code transmission, an information bit has added thereto a first redundant bit which is not evenly divisible by a generation polynomial expression even when all of the information bits are '0' or '1'. The code, including the information bits and the first redundant bit, is divided by the generation polynomial expression to provide a second redundant bit as the residue of such division, which is added to the information bit to provide a resultant code which is transmitted. The first redundant bit is added to the received code, which is then divided by the generation polynomial expression to detect the introduction of an error in the transmission path by the existence of a residue of the last division. An apparatus for accomplishing the above includes a dividing circuit consisting of a shift register having modulo 2 type adding circuits inserted between its adjacent stages in correspondence with constants of a generation polynomial expression and feedback paths extending from the shift register output to the adding circuits, a circuit for adding or presetting the first redundant bit in the shift register stage of the dividing circuit to which an information bit is applied, a circuit for providing the second redundant bit as the residue of a code, divided by the generation polynomial expression, and a circuit for adding the second redundant bit to the information bit, thereby providing the code to be transmitted.

Method and apparatus for detecting errors in a transmitted code

A video signal recorder/reproducer is used to record and/or reproduce pulse signals in successive tracks on a record medium. During recording, the pulse signals, which may, as one example, represent audio information, are interleaved with simulated horizontal and vertical synchronizing signals of the type similar to the synchronizing signals which normally are included in a composite video signal. During signal reproduction, the reproduced simulated horizontal and vertical synchronizing signals are detected and used to control the recovery of data from the reproduced pulse signals.

Video signal recorder/reproducer for recording and reproducing pulse

A power amplifier has an input terminal supplied with a PCM (pulse code modulated) signal and a plurality of power supplies, each producing a voltage weighted according to the order of bits of the PCM-code. Switching means are controlled by the PCM input signal to connect selective ones of the power supplies in series to a load in response to the PCM signal.

Digital to analog converter with power amplification

A pulse control circuit comprising a first FET (Field Effect Transistor), put into the conductive state in response to an input pulse signal, a first time constant circuit charged when the first FET is put in the conductive state, a second FET put into the conductive state with the charging voltage of the first time constant circuit, and a second time constant circuit discharging the charged electricity in the first time constant circuit when the second FET is put in the conductive state.

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Kawasaki, Japan

Akira Iga