Hitachi, Ltd.

Akira Ide

Masahiro Iwamura

Yutaka Kobayashi

Tatsumi Yamauchi

Atsushi Hiraishi

Takashi Akioka

Yuji Yokoyama

Shigeru Takahashi

Nobuyuki Gotou

Hideaki Uchida

Yoshikazu Saito

Goro Kitsukawa

Nozomu Matsuzaki

Kanji Oishi

Masahiro Yamamura

Yoji Idei

Masanori Odaka

Nobuo Tamba

Minoru Tateno

Koichi Motohashi

A 64Mb DRAM includes memory cell array areas , sense amplifier areas , subword driver areas , and cross areas . For each horizontal input/output line IOH paraleel to the word line W, throuh holes on the sense amplifiers provide connections between the second metal line hierarchy M and the third metal line hierarchy M . The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas . In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.

Semiconductor device

A 64 Mb DRAM includes memory cell array areas,, sense amplifier areas,, subword driver areas,, and cross areas,. For each horizontal input/output line IOH parallel to the word line W, through holes on the sense amplifiers provide connections between the second metal line hierarchy M,and the third metal line hierarchy M,. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas,in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas,. In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.

A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

Signal transition detector circuit

An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

Semiconductor integrated circuit having logi gates

A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

Semiconductor integrated circuit having logic gates

An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.

Microprocessor having high speed, low noise output buffers

High speed, low noise output buffer with non-identical pairs of output

A semiconductor integrated logic circuit is provided which includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, wherein each of the logic gates is coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. This arrangement is particularly effective for decoders in semiconductor memory circuits which use a common NMOS to receive one input for a plurality of logic decoder gates. An improved read/write arrangement is also provided for semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

A level conversion circuit having a plurality of switching elements connected in series or in parallel to a part thereof and having inputted a plurality of complementary signals to the plurality of switching elements connected in series or in parallel, and a high speed and high driving power switching circuit having a bipolar transistor which is directly driven by an output of such level conversion circuit and which provides level conversion and logic functions.

Switching circuit

An invention is disclosed, which is suitable for operating a bipolar-MOS logic circuit, and in particular Bi-CMOS logic circuit with a low power supply voltage below 5V, e.g. around 3V. According to the present logic circuit, since the base current of a second NPN transistor is supplied from a power supply through a PMOS transistor (first current switching means), the impedance of which is lowered previously by a logic inverting means and an NMOS logic circuit (second current switching means), which is on/off controlled by an input signal, in a transient logic level transition period where the output is switched from the level '1' to '0' (i.e. it falls), it is possible to supply a sufficient base current to the second NPN. In this way, it is possible to turn-on the second NPN with a high speed and to pull down to the level '0' with high speed. Further, since the PMOS is switched off owing to the action of the logic inverting means just after having allowed a sufficient base current flow therethrough, the current path, through which the base current of the second NPN is supplied, is stopped and thus DC power consumption is elimated.

Bipolar MOS logic circuit and semiconductor integrated circuit

A sense amplifier in a semiconductor memory device comprising a differential pair of bipolar transistors whose bases are supplied with read signals appearing on a pair of common data lines pulled up to the side of a positive power source potential, a regulated current circuit which causes a constant current to flow from the common emitters of the pair of bipolar transistors, as well as regulated current circuits which bias the respective bases of the pair of bipolar transistors to the side of a negative power source potential, and a control circuit which switches and controls the respective regulated current circuits in accordance with the select state of the sense amplifier, and also comprising saturation preventive circuits which cause minute currents to flow from the respective bases of the pair of bipolar transistors toward the negative power source potential, so that the bipolar transistors are avoided from falling into saturated states when the regulated current circuits are turned 'off,' thereby making it possible to reduce the average power consumption of the memory device without delaying the operating speed thereof.

Semiconductor memory device

A level conversion circuit having a plurality of switching elements connected in series or in parallel to a part thereof and inputted a plurality of complementary signals to the plurality of switching elements connected in series or in parallel, and a high speed and high driving power switching circuit having a bipolar transistor which is directly driven by an output of such level conversion circuit and which provides level conversion and logic functions.

BiMOS current mirror

In a semiconductor integrated circuit device, input protective elements have current limiting resistors which are diffused resistors of a second conductivity type formed in a first semiconductor region of a first conductivity type isolated electrically by a second semiconductor region of the second conductivity type, with the first conductivity type semiconductor region being in a floating state electrically. The input protective elements create less leak current and have high electrostatic durability.

Growing community of inventors

Takasaki, Japan

Akira Ide