Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Micron Technology Incorporated

Other

Longitude Semiconductor S.a.r.l.

Akira Ide

Riichiro Takemura

Tomonori Sekiguchi

Satoru Akiyama

Kayoko Shibata

Yasuhiro Takai

Hiroaki Nakaya

Satoshi Itaya

Shoji Azuma

Naoki Ogawa

Kentaro Hara

Yasuyuki Shigezane

Manabu Ishimatsu

Koji Torii

Chikara Kondo

Junichi Hayashi

Jun Sasaki

Akira Kotabe

Masahiro Yamaguchi

Masanori Yoshida

Hideyuki Yoko

Ryuji Takishita

Hideyuki Yokou

Homare Sato

Daisuke Tsuji

Takanori Eguchi

Kaoru Sonobe

Masahito Yamato

Hiroki Ichikawa

Takashi Asaoka

Shinji Furumi

Kenichi Tanamachi

Kazuo Hidaka

Embodiments of the disclosure are drawn to apparatuses and methods for testing the resistance of through silicon vias (TSVs) which may be used, for example, to couple multiple memory dies of a semiconductor memory device. A force amplifier may selectively provide a known current along a mesh wiring structure and through the TSV to be tested. The force amplifier may be positioned on a vacant area of the memory device, while the mesh wiring structure may be positioned in an area beneath the TSVs of the layers of the device. A chopper instrumentation amplifier may be selectively coupled to the TSV to be tested to amplify a voltage across the TSV generated by the current passing through the TSV. The chopper instrumentation amplifier may be capable of determining small resistance values of the TSV.

Apparatuses and methods for high sensitivity TSV resistance measurement circuit

Embodiments of the disclosure are drawn to apparatuses and methods for testing through silicon vias (TSVs) which may be used, for example, to couple layers of a semiconductor memory device. The TSVs and/or the die around the TSVs may require testing. A switch circuit may be used to selectively couple one or more test circuits to an amplifier. The test circuits may generate a voltage that is related to one or more parameters of the TSV being tested. The amplifier may amplify the voltage, which may be used to determine if the TSV passes the particular test determined by the test circuit selected by the switch circuit. The switch circuit and/or other components of the test circuits may be controlled by control signals to determine the operation of a particular test.

Apparatuses for selective TSV block testing

Embodiments of the disclosure are drawn to apparatuses and methods for a chopper instrumentation amplifier. For a variety of applications, such as testing the resistance of connections between layers of a memory, it may be desirable to provide a high gain instrumentation amplifier. A chopper instrumentation amplifier may provide a high gain while allowing a wide range of common input voltages and a canceling an offset on the amplifier. An example chopper instrumentation amplifier of the present disclosure may include a plurality of amplifiers including chopper amplifiers and non-chopper amplifiers. The chopper amplifiers may use chopper circuits to cancel out an offset voltage of the amplifiers. Low pass filters may be used to minimize the impact of the chopper amplifiers.

Apparatuses and methods for a chopper instrumentation amplifier

An apparatus including through substrate vias (TSVs) used to interconnect stacked chips is described. The apparatus according to an embodiment includes a plurality of first selection lines each extending in a first direction; a plurality of second selection lines each extending in a second direction to cross the plurality of first selection lines; and a plurality of a TSV units disposed in intersections of the plurality of first selection lines and the plurality of second selection lines, respectively. Each TSV unit of the plurality of TSV units includes a TSV; a switch coupled to the TSV; and a selection circuit. The selection circuit is configured to control a switching state of the switch responsive to each of an associated one of the plurality of first selection lines and an associated one of the plurality of second selection lines being set to an active level.

TSV redundancy and TSV test select scheme

A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.

Semiconductor device having plural memory chip

One current source includes a first transistor including a drain connected to an output terminal, and a source directly connected to a first power supply, a second transistor including a drain connected to a gate, the gate of the second transistor being connected to the gate of the first transistor, and a source directly connected to the first power supply, a third transistor opposite the first channel type including a drain connected to the drain of the second transistor, a fourth transistor including a drain connected to the source of the third transistor, a gate connected to a first bias voltage, and a source directly connected to second power supply voltage, and a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third transistor.

Constant current source circuit

A method for manufacturing a stacked semiconductor memory device includes testing a plurality of memory chips to detect first defective addresses, programming optical fuses with first defective address information on each of the plurality of memory chips that have the first defective addresses, stacking the plurality of memory chips, testing the stacked memory chips to detect second defective addresses, and programming electrical fuses with second defective address information.

Semiconductor device having optical fuse and electrical fuse

Disclosed herein is a device that includes: a semiconductor substrate; plurality of first through-substrate vias each penetrating through the semiconductor substrate, a plurality of second through-substrate vias each penetrating through the semiconductor substrate, an insulating film formed over the semiconductor substrate, the insulating film including a first opening and a plurality of second openings, the first opening being located over the first through-substrate vias, and each of the second openings being located over a corresponding one of the second through-substrate vias.

Semiconductor device having penetrating electrodes each penetrating through semiconductor chip

Disclosed herein is an apparatus that includes a first semiconductor chip including a first electrode, and a second semiconductor chip including a second electrode connected to the first electrode. One of the first and second semiconductor chips includes a first temperature sensor circuit generating a first detection signal, the first detection signal taking a first level when a temperature is equal to or higher than a first temperature, the first detection signal taking a second level when the temperature is lower than the first temperature; and a first delay code generation circuit outputting a first delay code signal in response to the first level of the first detection signal, and outputting a second delay code signal different from the first delay code signal in response to the second level of the first detection signal.

Semiconductor device capable of performing a read leveling and a write leveling based on an ambient temperature

A current source includes a first MOS transistor of a first channel type including a drain connected to an output terminal, and a source directly connected to a first power supply, a second MOS transistor of the first channel type including a drain connected to a gate, the gate of the second MOS transistor being connected to the gate of the first transistor, and a source directly connected to the first power supply, a third MOS transistor of a second channel type opposite the first channel type including a drain connected to the drain of the second MOS transistor, a fourth MOS transistor of the second channel type including a drain connected to the source of the third MOS transistor, a gate connected to a first bias voltage, and a source directly connected to second power supply voltage, and a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third MOS transistor.

Disclosed herein is a device including a first semiconductor chip having a first internal circuit formed in a first substrate, and a plurality of penetrating electrodes each penetrating through the first semiconductor substrate. The plurality of penetrating electrodes includes first, second, third and fourth penetrating electrodes arranged along a first line. The first and second penetrating electrodes are in a floating state without being electrically connected to the first internal circuit. The third penetrating electrode is electrically connected to a first power supply line that conveys a first power supply potential to the first internal circuit. The fourth penetrating electrode is electrically connected to a second power supply line that conveys a second power supply potential to the first internal circuit. The third and fourth penetrating electrodes are arranged between the first penetrating electrode and the second penetrating electrode.

Semiconductor device having penetrating electrodes each penetrating through substrate

A semiconductor device includes a semiconductor substrate having a peripheral edge, a first surface, and a second surface opposite to the first surface, an inter-layer insulator including a guard ring formed on the first surface, adjacent to the peripheral edge of the semiconductor substrate, a first groove formed on the second surface, adjacent to the peripheral edge of the semiconductor substrate, and a through electrode penetrating the second surface to the inter-layer insulator near the groove and on an opposite side of the groove with respect to the peripheral edge.

Semiconductor device including guard ring and groove

Growing community of inventors

Tokyo, Japan

Akira Ide