Kabushiki Kaisha Toshiba

International Business Machines Corporation

Toshiba Memory Corporation

Akira Hokazono

Yoshiyuki Kondo

Hiroshi Itokawa

Tenko Yamashita

Veeraraghavan S Basker

Chun-chen Yeh

Kazunari Ishimaru

Mariko Takayanagi

Masakazu Goto

Yoshiaki Toyoshima

Hiroyuki Kutsukake

Satoshi Inaba

Tatsuya Ohguro

Makoto Fujiwara

Yusuke Arayashiki

Shigeru Kawanaka

Kazuya Ohuchi

Nobuyuki Momo

Toshitaka Miyata

Takeo Nakayama

Hiroki Okamoto

Motohiko Fujimatsu

Kanna Tomiye

A storage device includes: a substrate; a first conductive layer extending in a first direction; a second conductive layer adjacent to the first conductive layer in a second direction, and extending in the first direction; a third conductive layer extending in a third direction; a fourth conductive layer extending in the second direction; a fifth conductive layer disposed on the second conductive layer, extending in the third direction, and being electrically connected to the fourth conductive layer; a first storage layer disposed between the third conductive layer and the fourth conductive layer; a first semiconductor layer disposed between the first conductive layer and the third conductive layer; a second semiconductor layer disposed between the second conductive layer and the fifth conductive layer; and a first gate electrode extending in the second direction and being shared by side surfaces of the first semiconductor layer and the second semiconductor layer.

Storage device

A memory device includes a first interconnect extending in a first direction, a first and a second semiconductor members extending in a second direction, a first and a second gate lines extending in a third direction, a second and a third interconnects extending in the second direction. The first and the second semiconductor members are arranged along the first direction, with first ends in the second direction connected to the first interconnect. The second interconnect is connected to a second end in the second direction of the first semiconductor member. The third interconnect is connected to a second end in the second direction of the second semiconductor member. The distance between the first interconnect and the first gate line is longer than the distance between the first interconnect and the second gate line.

Memory device

Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.

Stressed channel bulk fin field effect transistor

According to one embodiment, a tunnel FET includes a semiconductor region of a first conductivity type, a gate electrode provided on a surface portion of the semiconductor region via a gate insulating film, a source region provided in the semiconductor region on one side of the gate electrode, and a drain region provided in the semiconductor region on the other side of the gate electrode. The source region is a region of either the first conductivity type or a second conductivity type having a higher impurity concentration than the semiconductor region of the first conductivity type. The drain region includes a Schottky barrier junction.

Tunnel FET

In one embodiment, a semiconductor device includes a semiconductor substrate, and first and second transistors of first and second conductivity types on the substrate. The first transistor includes a first gate electrode on the substrate, a first source region of the second conductivity type and a first drain region of the first conductivity type disposed to sandwich the first gate electrode, and a first channel region of the first or second conductivity type disposed between the first source region and the first drain region. The second transistor includes a second gate electrode on the substrate, a second source region of the first conductivity type and a second drain region of the second conductivity type disposed to sandwich the second gate electrode, and a second channel region disposed between the second source region and the second drain region and having the same conductivity type as the first channel region.

Semiconductor device

In one embodiment, a semiconductor device includes a first diffusion layer of a first conductive type and a second diffusion layer of a second conductive type which is a reverse conductive type of the first conductive type, the first conductive type first diffusion layer and the second conductive type diffusion layer being spaced apart and provided in a semiconductor layer, a pocket region of the second conductive type which is provided on a surface portion of the semiconductor layer adjacently to the first diffusion layer, and a first extension region of the first conductive type which is provided in the semiconductor layer to cover at least a portion of the pocket region. A second diffusion layer side end portion of the first extension region is positioned closer to a second diffusion layer side than a second diffusion layer side end portion of the pocket region.

Semiconductor device and method for manufacturing the same

In one embodiment, a first main terminal region of a first conductivity type and a second main terminal region of a second conductivity type, which is an opposite conductivity type of the first conductivity type, formed in the semiconductor substrate so as to sandwich a gate electrode, a diffusion layer of the second conductivity type coming in contact with the first and second element isolation insulator films and having an upper surface in a position deeper than lower surfaces of the first and second main terminal regions, a first well region of the first conductivity type formed between the first main terminal region and the diffusion layer, and a second well region of the first conductivity type formed between the second main terminal region and the diffusion layer. The second well region has a impurity concentration higher than that of the first well region.

Semiconductor device and method of manufacturing the same

According to one embodiment, a pass gate provided between a data holding unit of an SRAM cell and a bit line, includes a first tunnel transistor and a first diode connected in series between the data holding unit and the bit line, and a second tunnel transistor and a second diode connected in series between the data holding unit and the bit line and connected in parallel to the first tunnel transistor and the first diode. Gate electrodes of the first tunnel transistor and the second tunnel transistor are connected to a word line. The first diode and the second diode have rectification in mutually opposite directions between the data holding unit and the bit line.

Pass gate, semiconductor memory, and semiconductor device

In one embodiment, a semiconductor device includes a substrate, a gate insulator on the substrate, and a gate electrode on the gate insulator. The device further includes a source diffusion layer of a first conductivity type and a drain diffusion layer of a second conductivity type disposed on a surface of the substrate so as to sandwich the gate electrode. The device further includes a junction forming region disposed between the source diffusion layer and the drain diffusion layer so as to contact the source diffusion layer. The junction forming region includes a source extension layer of the first conductivity type, a pocket layer of the second conductivity type above the source extension layer, and a diffusion suppressing layer disposed between the source extension layer and the pocket layer and containing carbon so as to suppress diffusion of impurities between the source extension layer and the pocket layer.

Semiconductor device and method of manufacturing same

In one embodiment, a semiconductor device includes a first diffusion layer of a first conductivity type and a second diffusion layer of a second conductivity type that are provided in a semiconductor layer at a distance, the second conductivity type being an opposite conductivity type of the first conductivity type, a first insulating film and a second insulating film that are provided on the semiconductor layer between the first diffusion layer and the second diffusion layer at a distance, a gate electrode provided on the first insulating film, and a threshold regulating electrode provided on the second insulating film.

Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.

Needle-shaped profile finFET device

Structures and methods are presented relating to formation of finFET semiconducting devices. An approach is presented to facilitate formation of a pMOS finFET which can be combined with a nMOS finFET to form a balanced CMOS device. A Si:C layer can be utilized to suppress diffusion of group III and group V impurities, where suppression can utilize interstitial and substitutional phases. A Si:Ge layer can be utilized to facilitate determination of transition between a Si layer and a Si:C layer to enable a finFET to be formed having a required volume of fin material exposed for anticipated operation (e.g., a target Vth) of the finFET device.

FinFET comprising a punch-through stopper

A semiconductor device according to one embodiment includes: a semiconductor layer formed on a semiconductor substrate; a gate electrode formed on the semiconductor layer via a gate insulating film; an impurity diffusion suppression layer formed between the semiconductor substrate and the semiconductor layer and including a C-containing Si-based crystal containing a first impurity, the C-containing Si-based crystal being configured to suppress diffusion of a second impurity having a p-type conductivity type, and the C-containing Si-based crystal with the first impurity having a function of suppressing generation of fixed charge in the C-containing Si-based crystal; and p-type source/drain regions formed in the semiconductor substrate, the impurity diffusion suppression layer and the semiconductor layer in sides of the gate electrode, the p-type source/drain region having an extension region in the semiconductor layer and containing the second impurity.

Semiconductor device including a p-type transistor having extension regions in sours and drain regions and method of fabricating the same

A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; Si:C layers formed on the semiconductor substrate in sides of the gate electrode; p-type source/drain regions formed in sides of the gate electrode in the semiconductor substrate, and a part of the p-type source/drain regions being formed in the Si:C layers; and silicide layers formed on the Si:C layers.

Growing community of inventors

Sagamihara, Japan

Akira Hokazono