Fujitsu Corporation

Akira Hattori

Takamitsu Tsuchimoto

Minoru Koshino

Hidehiko Nishida

Masanori Takahashi

Akio Shinagawa

Terutaka Tateishi

Yukio Sohma

Hiromu Hayashi

Yasuhiro Nara

Tsuyoshi Shinogi

The present invention relates to an access request control apparatus and more specifically to an apparatus for determining priority between a plurality of access requests in a memory control apparatus which uses a pipeline. One of the access requests from a plurality of channel processing devices CHP's is selected by a first priority determination circuit. The selected CHP request, the requests from a plurality of central processing units and the request in the loop-back of the pipeline control circuit are considered for selection by a second priority determination circuit. In case a CHP request, selected by the first priority determination circuit, is not selected by the second priority determination circuit or selected but nullified in the course of the pipeline, the CHP request is returned to the first priority determination circuit. But, in this case, a higher priority is given to the CHP request in the first priority determination circuit. In addition, the priority algorithm in the second priority determination circuit considers the kinds of operations of each access request and highly efficient memory access control can be realized.

Access request control apparatus which reassigns higher priority to

Data processing system having hierarchical memories

This invention relates to a system for processing access requests issued from a plurality of access requesting units to a memory. In particular, in a storage system where the buffer storage BS and main storage MS are provided, access is first made to BS based on and access request and if the desired data is not found in BS, access is made to MS. When the desired data is not found in BS and access is then made to MS, acces to BS is carried out based on the next access request from the same access requesting unit in parallel with the access to MS by the first access request.

Access control processing system in computer system

The present invention discloses a data processing system having a program structure and execution mode where an actual argument is bound to a formal argument of a function to be called by storing a pair of a variable name as the formal argument and a variable as the actual argument into a First-In-Last-Out type stack memory which is an environment list, the function called executes processings using a latest bind value of said environment list when referring to variable values, when a value of such function is obtained, the function value is returned by deleting the formal argument variable of the function from the environment list. The system includes an associative buffer memory provided externally to the stack memory, where at least the variable name and location data of variable on the environment list are stored in the associative buffer memory, and thereby the access time for referring to variables stored in the stack memory can be curtailed.

Stack machine with improved cache memory for variables

Effective expansion of a common intermediate buffer memory by equivalent use of the buffer memory in each CPU in a multiprocessor system. A method and system for achieving buffer memory coincidence is applied to a multiprocessor system provided with central processing units, buffer memories contained in respective central processing units, a main memory, and an intermediate buffer memory connected between the main memory and the buffer memories, wherein a buffer invalidation address information (BIA GO) is sent from the intermediate buffer memory to the i-th central processing unit (BIA GO #i) in accordance with the following logical expression:

System and method for achieving buffer memory coincidence in a

A method of operating an associative memory, which is provided for storing information, comprises the steps of extracting necessary information by means of access to said associative memory and updating information retained in the associative memory. In the method and system of the present invention, said associative memory comprises a data portion for storing a plurality of block information units as one module information unit, and an address array portion for storing a module address corresponding to said one module information unit, said associative memory further containing valid information arranged in conjunction with said module address in said address array portion for indicating which of said plural block information units constituting said one module information units is valid. Further, an address, with respect to which said associative memory is retrieved, is subjected to access to the address portion of said associative memory in a field shifted from a field in which said address is compared with an address read out from said address portion, and valid information is allotted in a least significant bit to each of said block information so as to obtain an increased capacity for said associative memory, and updating of information stored in said data portion is carried out in the block information unit.

Method and system for operating an associative memory

Described is an error-correcting and error-detecting system including a check-bits generating circuit which is formed in accordance with a (k,l) type check matrix, such (k,l) type check matrix being formed from an (m,l) type reference sub-matrix (where m&lt;k) and one or more (m,l) type sub-matrices, and each of the (m,l) type sub-matrices being derived from the (m,l) type reference sub-matrix by replacing unit-matrices of the (m,l) type reference sub-matrix with each other in accordance with a circular shift; wherein a desired check-bits code of an input data is obtained by multiplying the input data with respective reference sub-matrix and sub-matrices and by rearranging respective multiplied results produced from the respective rows of these reference sub-matrix and sub-matrices.

Error-correcting and error-detecting system

In a data processing system having an intermediate buffer memory provided between a large space main memory and small space, high speed buffer memories of a plurality of processors, a data block of the intermediate buffer memory to be replaced with a data block of the main memory is determined by utilizing LRU (Least Recently Used) algorithm as well as copy flags employed in buffer invalidation processing. In the intermediate buffer memory, a data block that the number of its copy flags in the ON state is smaller than any other data blocks, is selected as the data block to be replaced. The fact that the number of copy flags in the ON state implies that the data block is not frequently used by the processors. Replacement of such a data block alleviates the burden of the buffer invalidation processing imposed on the intermediate buffer memory.

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Yokohama, Japan

Akira Hattori