Micron Technology Incorporated

Lodestar Licensing Group LLC

Akira Goda

Kishore Kumar Muchherla

Eric N Lee

Huai-Yuan Tseng

Jonathan Scott Parry

Dave Scott Ebsen

James Fitzpatrick

Jeffrey S McNeil, Jr

Tomoharu Tanaka

Violante Moschiano

Dung Viet Nguyen

Vivek Shivhare

Sivagnanam Parthasarathy

Jiangli Zhu

Jung Sheng Hoei

Fangfang Zhu

Sanjay Subbarao

Haitao Liu

Peter Sean Feeley

Ugo Russo

Niccolo' Righetti

Nicola Ciocchini

Animesh Roy Chowdhury

Kunal R Parekh

Mustafa Nazmi Kaynak

Kamal M Karda

David Scott Ebsen

Lakshmi Kalpana Vakati

Giovanni Maria Paolucci

Gurtej S Sandhu

Sanh D Tang

Aaron S Yip

Patrick Robert Khayat

Koichi Kawai

Sundararajan Sankaranarayanan

Guangyu Huang

Litao Yang

Silvia Beltrami

Niccolo′ Righetti

Sead Zildzic, Jr

Yoshiaki Fukuzumi

Sampath K Ratnam

Krishna Kumar Parat

Mark Alan Helm

Ching-Huang Lu

Paolo Tessariol

Jun Fujiki

Yoshihiko Kamata

Michele Incarnati

Jeremy Binfet

Walter Di Francesco

Xiangyu Tang

Giuseppina Puzzilli

Umberto Siciliani

Daniel J Hubbard

Suresh Rajgopal

Khaled Hasnat

Shafqat Ahmed

Yifen Liu

Paing Z Htet

Mojtaba Asadirad

Marc Aoulaiche

Junwyn A Lacsao

Jin Chen

Eric Nien-Heng Lee

Haibo Li

Safqat Ahmed

A memory device includes a memory array including wordlines and at least one string of cells. Each cell of the at least one string of cells is addressable by a respective wordline. The memory device further includes control logic, operatively coupled to the memory array, to perform operations including generating gate-induced drain leakage (GIDL) with respect to the at least one string of cells, and causing a grounding voltage to be applied to a set of wordlines to ground each cell of the at least one string of cells addressable by each wordline of the set of wordlines. The grounding voltage applied to the set of wordlines enables transport of positive charge carriers generated by the GIDL. In some embodiments, the positive charge carriers neutralize a buildup of negative charge carriers generated during a seeding phase of a program refresh operation.

Program refresh with gate-induced drain leakage

Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.

Buffer allocation for reducing block transit penalty

Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

Multiple-pass programming of memory cells using temporary parity generation

Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.

Temporary parity buffer allocation for zones in a parity group

A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data in a first memory device of a plurality of memory devices. A cached data item on a second memory device of the plurality of memory devices is identified. A valid-to-invalid ratio of the victim MU is compared to a threshold value. In view of comparison, it is determined whether to pad the cached data item with at least a subset of the valid data stored at the victim MU or dummy data. Based on the determination, the cached data item padded with one of at least a subset of the valid data stored at the victim MU or the dummy data is written to a target MU.

Padding cached data with valid data for memory flush commands

A memory device comprises an array of memory cells organized into a plurality of wordlines, and a processing device to perform processing operations that receive a program command specifying a memory unit and data comprising first received data, where the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines. The processing operations also program the specified data to the memory unit by programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, and programming the first data pattern to the first retired boundary wordline.

Selectively programming retired wordlines of a memory device

A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The processing device is further to receive a second read command at a second time. The processing device is further to determine that the first read command and the second read command are directed to an at least partially same set of memory cells of the plurality of memory cells. The processing device is further to perform a media management operation with respect to the at least partially same set of memory cells.

Modified read counter incrementing scheme in a memory sub-system

A read is initiated with respect to a target cell. A pair of adjacent cells includes a first cell and a second cell each adjacent to the target cell. First cell state information is obtained for the first cell and second cell state information is obtained for the second cell. A state information bin is determined by applying a pre-defined operation to the first cell state information and the second cell state information of the respective pair of adjacent cells. The target cell is assigned to the state information bin. Each state information bin defines a read level offset for reading the target cell.

Corrective reads with improved recovery from data retention loss

An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.

Memory devices with backside bond pads under a memory array

Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.

Adaptive pre-read management in multi-pass programming

Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array, the block comprising a plurality of wordlines, wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines concurrently and senses a level of current flowing through the sacrificial string while the read voltage is applied. In addition, the control logic identifies, based on the level of current flowing through the sacrificial string, whether a threshold level of read disturb has occurred on the block.

Sacrificial strings in a memory device to detect read disturb

A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.

Write-once memory encoded data

A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including reading a first copy of data stored in a first set of memory cells comprising a first memory cell, determining whether a threshold voltage of the first memory cell is within a first range of threshold voltages, responsive to determining that the threshold voltage of the first memory cell is within the first range of threshold voltages, reading a second copy of the data stored in a second set of memory cells comprising a second memory cell, determining whether a threshold voltage of the second memory cell is within a second range of threshold voltages, and responsive to determining that the threshold voltage of the second memory cell is outside the second range, using the second copy of the data.

Using duplicate data for improving error correction capability

A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.

Memory programming using consecutive coarse-fine programming operations of threshold voltage distributions

A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Memory device programming technique for increased bits per cell

Growing community of inventors

Tokyo, Japan

Akira Goda