Micron Technology Incorporated

Intel Corporation

Other

Akira Goda

Krishna Kumar Parat

Haitao Liu

Giuseppina Puzzilli

Mark Alan Helm

Carmine Miccoli

Kishore Kumar Muchherla

Jeremy Binfet

Todd A Marquart

Seiichi Aritome

Jeffrey S McNeil, Jr

Gil Golov

Yijie Zhao

Pranav Kalavade

Guangyu Huang

Chandra V Mouli

Sanh D Tang

Koji Sakui

Violante Moschiano

John David Hopkins

Doyle W Rivers

Niccolo' Righetti

Shafqat Ahmed

Changhyun Lee

Toru Tanzawa

Kamal M Karda

Shigekazu Yamada

Roger W Lindsay

Christian Caillat

Aurelio Giancarlo Mauri

Fatma Arzum Simsek-Ege

Justin B Dorhout

Han Zhao

Khaled Hasnat

Minsoo Lee

Niccolo′ Righetti

Tomoharu Tanaka

Peter Sean Feeley

Koichi Kawai

Prashant S Damle

Zhenyu Lu

Alessandro Torsi

William C Filipiak

Carlo Musilli

Gurtej S Sandhu

Charles H Dennison

Kunal R Parekh

Tommaso Vali

Andrei Mihnea

Paolo Tessariol

Albert Fayrushin

Ian C Laboriante

Ramey M Abdelrahaman

Benben Li

Taehoon Kim

Roger Porter

Lifang Xu

Zengtao T Liu

Andrew Bicksler

Yushi Hu

Augusto Benvenuti

Luca Laurin

Charan Srinivasan

Mason A Jones

Kalpana Vakati

Durai Vishak Nirmal Ramaswamy

Sivagnanam Parthasarathy

Sampath K Ratnam

Aaron S Yip

Karthik Sarpatwari

Graham Richard Wolstenholme

Shyam Surthi

Richard J Hill

Sundararajan Sankaranarayanan

Byeung Chul Kim

Hiroyuki Sanda

Tejas Krishnamohan

Ankit Sharma

Tyson M Stichka

Brian J Soderling

Arnaud A Furnemont

Mustafa Nazmi Kaynak

Patrick Robert Khayat

Eric N Lee

Jian Li

Kevin Roy Brandt

Deepak Chandra Pandey

Shantanu R Rajwade

Litao Yang

Yifen Liu

Marc Aoulaiche

Mojtaba Asadirad

Michael G McNeeley

Jin Chen

Eric Nien-Heng Lee

Niccolo Righetti

Aurielo Giancarlo Mauri

Koichi Kawal

Andrew Bickler

A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

Driver placement in memories having stacked memory arrays

Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material

A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

Partitioned memory having error detection capability

A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.

Using duplicate data for improving error correction capability

A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

Separate partition for buffer and snapshot memory

Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

Sequential voltage ramp-down of access lines of non-volatile memory device

A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.

Partitions within snapshot memory for buffer and snapshot memory

A method includes during a first portion of a service life of a memory device, programming at least one memory cell of the memory device to a first threshold voltage corresponding to a desired data state. The method can include during a second portion of the service life of the memory device subsequent to the first portion of the service life of the memory device, programming at least one memory cell of the memory device to a second threshold voltage corresponding to the desired data state. The second threshold voltage can be different than the first threshold voltage.

Threshold voltage based on program/erase cycles

Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

Multi-decks memory device including inter-deck switches

A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

Methods of forming microelectronic devices, and related microelectronic devices and electronic systems

Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

Memory devices having source lines directly coupled to body regions and methods

A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

Read voltage calibration for copyback operation

A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.

Threshold voltage distribution adjustment for buffer

Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.

Partial block memory operations

Growing community of inventors

Boise, ID, United States of America

Akira Goda