Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Ulsi Engineering Corp.

Other

Hitachi Engineering Co., Ltd.

Akira Fukami

Shuji Ikeda

Toshiaki Yamanaka

Akihiro Shimizu

Kazushige Sato

Shinichiro Mitani

Kenichi Kikushima

Masaya Iida

Atsuo Watanabe

Atsushi Hiraishi

Osamu Saito

Takahide Ikeda

Katsumi Ogiue

Masanori Odaka

Nobuo Tamba

Mitsuru Hirao

Masayuki Ohayashi

Kouichirou Yamada

Tadashi Kuramoto

Yutaka Kobayashi

Takahiro Nagano

Yoshiaki Yazawa

Takaya Suzuki

Kenichi Shoji

A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Semiconductor integrated circuit device and process for manufacturing the same

A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Semiconductor integrated circuit device and process for manufacturing

Growing community of inventors

Higashimurayama, Japan

Akira Fukami