Fujitsu Corporation

Fuji Photo Film Company, Limited

National Institute of Information and Communications Technology, Incorporated

Akira Endoh

Yoshimi Yamashita

Keiji Ikeda

Masahiro Morikawa

Hiroshi Arimoto

Shigehiko Sasa

Issei Watanabe

A compound semiconductor device includes a compound semiconductor layer, a gate electrode disposed above the compound semiconductor layer, and source and drain electrodes disposed above the compound semiconductor layer with the gate electrode between the source and drain electrodes, wherein the compound semiconductor layer has a groove in a surface thereof at least between the source electrode and the gate electrode in a region between the source electrode and the drain electrode, the groove gradually deepened toward the source electrode.

Compound semiconductor device

A semiconductor device includes a semiconductor stacked structure including at least an electron transit layer and an electron supply layer over a substrate. The electron supply layer includes a first portion and second portions sandwiching the first portion, and the first portion has a higher energy of a conduction band than that of the second portion, and includes a doped portion doped with an n-type impurity and undoped portions that sandwich the doped portion and are not doped with an impurity.

Semiconductor device with electron supply layer

A semiconductor device includes: a semiconductor multi-layer structure which includes at least an electron traveling layer and an electron supply layer on a substrate, wherein the electron supply layer includes a first portion which contains Sb and has at least a portion doped with Te, and a second portion which is located closer to the electron traveling layer side than the first portion and has a lattice constant smaller than that of the first portion.

Semiconductor device

A semiconductor device includes a first semiconductor layer provided over a substrate; an electron transit layer contacting a top of the first semiconductor layer; and a second semiconductor layer contacting a top of the electron transit layer, wherein the electron transit layer has a dual quantum well layer having a structure where a first well layer, an intermediate barrier layer, and a second well layer are sequentially stacked, an energy of a conduction band of the intermediate barrier layer is lower than an energy of conduction band of the first semiconductor layer and the second semiconductor layer, and a ground level is generated in the first and second well layers, and a first excitation level is generated in the dual quantum well layer.

A semiconductor device includes: an electron transit layer formed with a semiconductor material, the electron transit layer being formed on a semiconductor substrate; an n-type semiconductor layer formed with a semiconductor material having a wider bandgap than the electron transit layer, the n-type semiconductor layer being formed on the electron transit layer; a &#x3b4; doping area having an n-type impurity doped in a sheet-shaped region, the &#x3b4; doping area being formed on the n-type semiconductor layer; and a barrier layer formed with a semiconductor material having a wider bandgap than the electron transit layer, the barrier layer being formed on the &#x3b4; doping area.

A channel layer () made of compound semiconductor and a barrier layer () made of compound semiconductor having a band gap wider than the channel layer are formed over a substrate. A gate insulating film () made of first insulating material is formed on the barrier layer over the channel region. A gate electrode () is formed on a partial area of the gate insulating film. A protective film is disposed on the gate insulating film on both sides of the gate electrode. The protective film comprises a lower protective film () made of second insulating material whose etching resistance is different from the first insulating material and an upper protective film () made of third insulating film whose etching resistance is different from the second insulating material. A source electrode and a drain electrode are electrically connected to the channel layer on both sides of the gate electrode.

Semiconductor device having MIS structure and its manufacture method

In a nitride-system semiconductor, being different from GaAs and Si, Schottky barrier heights &#x3a6;change significantly against work functions &#x3a6;of metals. Then, for example, on an HEMT in which a buffer layer and a barrier layer constituted by nitride-system semiconductors are sequentially formed on a substrate, and a gate electrode is formed on the barrier layer, when a metal having a relatively large work function &#x3a6;is selected as a metal constituting the gate electrode, and the thickness of the barrier layer is adjusted so that the Schottky barrier height &#x3a6;becomes larger as compared to a semiconductor surface potential &#x3a6;on both sides of the gate electrode, a two-dimensional electron gas cannot exist below the gate electrode even when no recess is formed on a portion immediately beneath the gate electrode on the barrier layer, so that the enhancement operation becomes possible.

Semiconductor device and method for manufacturing the same

A process for multi-layer, co-coating preparation of a silver halide color light sensitive material comprising co-coating at least eight coating liquid compositions simultaneously onto a traveling support to form at least eight total layers comprising a lowermost layer adjacent to the support and at least seven outer layers adjacent to the lowermost layer, wherein the at least eight coating liquid compositions comprise a lowermost layer coating liquid composition and at least seven outer coating liquid compositions; the lowermost layer coating liquid composition has a viscosity of 15 to 100 cp; each outer layer coating liquid composition of the at least seven outer layer liquid compositions has a viscosity of at least 30 cp; and the at least seven outer layer coating liquid compositions have an arithmetic mean viscosity of 60 to 300 cp.

Process for preparing color light-sensitive material by multi layer

A quantum interference effect transistor comprising a semiconductor substrate, an n-type first semiconductor layer, a channel second semiconductor layer, an n-type third semiconductor layer, a gate electrode, a source electrode, a drain electrode, a source region and a drain region, said second semiconductor layer having an electron affinity larger than that of the first and third layers to generate a two dimensional electron gas channel, characterized in that the channel second layer between the source and drain regions consists of lead portions and a middle portion sandwiched with them, and in the middle portion the channel is divided into two channel passages without forming a separation layer in the second layer. The first, second and third layers form a quantum well structure. The middle portion of the second layer is thicker than the lead portions, so that a quantum well width at the middle portion is wider and has a larger amount of bending of a conduction band bottom Ec to divide an electron probability distribution into two parts with peaks.

Growing community of inventors

Machida, Japan

Akira Endoh