Lapis Semiconductor Co., Ltd.

Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Akira Akahori

Katsuaki Matsui

A voltage generating circuit, a semiconductor memory device, and a voltage generating method are provided. The voltage generating circuit includes: an oscillation signal generating part generating an oscillation signal that alternately repeats a state of a first voltage and a state of a second voltage; a capacitor having one end receiving the oscillation signal and an other end connected to an output node; a switch element receiving a control voltage and set to an on state or an off state according to the control voltage, and applying the first voltage to the output node when set to the on state; and a switch control part supplying, as the control voltage to the switch element, the second voltage when the oscillation signal is in the state of the first voltage, and a voltage of the output node when the oscillation signal is in the state of the second voltage.

Voltage generating circuit, semiconductor memory device, and voltage generating method

A write voltage generation circuit includes: a power supply terminal that receives an external power supply voltage; a boosting circuit that boosts the external power supply voltage to generate a boosted voltage; and a selector that selects either one of the external power supply voltage and the boosted voltage, and outputs the selected voltage as the write voltage. The selector selects the external power supply voltage as the write voltage in a first part of a write period for writing data to a memory cell, and selects the boosted voltage as the write voltage in a latter part of the write period.

Write voltage generation circuit and memory apparatus

Semiconductor memory including a reference amplifier and a high-speed start-up circuit having four FETs. The reference amplifier supplies the reference voltage to a sense amplifier via a reference voltage supply line. The high-speed startup circuit has four FETs. The first FET is turned on to apply a first voltage onto a first line when the enable signal indicates deactivation. The second FET is turned on to apply ground potential onto the first line when the voltage on the reference voltage supply line is higher than a gate threshold voltage value. The third FET is turned on to generate the first voltage when the enable signal indicates activation. The fourth FET is turned off when the first line is at ground potential and is turned on to supply the first voltage from the third FET onto the reference voltage supply line when the first voltage is applied onto the first line.

Semiconductor memory

A semiconductor integrated circuit having a test circuit for inspecting states of connections between a plurality of pads and respective external terminals by bonding wires. The test circuit comprises, for each of a plurality of pads, a control terminal provided to receive a control signal of a logic level equal to the logic level of a signal applied to a corresponding one of the external terminals, an inverter which inverts the logic level on the control terminal, an inverted output terminal of the inverter being connected to the pad via a connection line; and an exclusive-NOR gate which outputs an exclusive NOR of the logic level on the connection line and the logic level on the control terminal.

Semiconductor integrated circuit

In a flip-flop circuit where latched complementary signals of first and second output terminals are inverted by complementary first and second input pulses, the conductivity of a first load transistor connected to the first output terminal is controlled by the signal from the second output terminal, and the conductivity of a second load transistor connected to the second output terminal is controlled by the signal from the first output terminal.

Flip-flop circuit and frequency divider using the flip-flop circuit

A complementary pass-transistor logic includes input nodes provided with first complementary signals; intermediate nodes for outputting complementary intermediate signals; a logic network comprised of NMOS transistors, the network being connected between the input nodes and the intermediate nodes, and the conduction states of the transistors being controlled by second complementary input signals to output a logical operation result of the first and second input signals to the intermediate nodes; and inverters for inverting the intermediate signals and producing complementary output signals, wherein the NMOS transistors of the logic network are configured as a depletion-type NMOS.

Growing community of inventors

Tokyo, Japan

Akira Akahori