Sanyo Electric Co., Ltd.

Akiomi Kunisa

Nobuo Itoh

Seiichiro Takahashi

Yoshihiro Hori

Toshiaki Hioki

Satoshi Sumi

Noboru Mamiya

Kenji Nakao

Kenji Torazawa

Kenji Asano

Hisashi Matsuyama

Yoshiharu Uchihara

An encoding apparatus that embeds a watermark in host data is provided. A multiplexer generates a plurality of bit sequences by adding initial data to the head of the watermark. A scrambler scrambles a plurality of the bit sequences respectively and generates a plurality of scrambled watermarks. An embedder embeds a plurality of the scrambled watermarks in the host data and generates a plurality of candidate watermarked host data. A signal-to-noise ratio calculator evaluates the robustness of the watermarks hidden in the respective candidate watermarked host data. A selector selects one candidate that has the highest level of the robustness as a final watermarked host data.

Digital watermarking system using scrambling method

A digital watermark extracting apparatus that extract a watermark hidden in host data is provided. A location information generator generates a plurality of candidate watermark locations according to a secret key. An extractor extracts from each of the candidate watermark locations a watermark which has been embedded in a watermarked host signal and detects a soft decision value on the extracted watermark. A decision value evaluator evaluates a sum of the absolute values of the components of the each soft value. A selector determines a true watermark location according to the soft decision value evaluated by the decision value evaluator. The selector provides to an ECC decoder the soft decision value on the watermark extracted from the true watermark location. The ECC decoder error-correction decodes the soft decision value on the extracted watermark and outputs watermark information.

A digital watermarking apparatus that embeds two watermarks in host data is provided. The first watermarking block generates a plurality of watermarking location candidates of the first watermark, and embeds the first watermark into the respective location candidates of the host data, and then selects one candidate with a high level of robustness as the first watermarked host data. The second watermarking block scrambles the watermarking location information on the first watermark and thereby generates a plurality of the second watermark candidates. Then the second watermarking block embeds the respective second watermark candidates in the first watermarked host data and selects one candidate with a high level of robustness as the second watermarked host data.

Multilayered digital watermarking system

A digital modulation method in which at a head of an input block (pre-translation), each of a plurality of different types of initial data of t bits is multiplexed to generate a plurality of different types of multiplexed blocks, t bits at the head and immediately following t bits of each of the multiplexed blocks are subjected to exclusive OR operation, the immediately following t bits are replaced by the result of operation, the replaced t bits and the immediately following t bits are subjected to an exclusive OR operation, and the immediately following t bits are replaced by the result of operation, and thereafter in the similar manner, a convolution operation is executed. A plurality of different types of translated blocks are produced by the convolution operation, and DC components of thus provided translated blocks are calculated, respectively, absolute values of the respective DC components are compared with each other, and a translated block having the minimum value is selected and output externally.

Method and circuit for digital modulation and method and circuit for digital demodulation

A meandering groove is formed in a digital disk (,) with a wobble signal that is wobbled to reproduce a clock signal. The wobble signal is read out by an optical head (,). An address detection circuit (,) detects an address signal that is multiplexed with the wobble signal. A PLL oscillation circuit (,) provides a clock signal in synchronization with the wobble signal. Data is modulated by a modulation circuit (,) according to the clock signal and a timing signal based on the address signal, and recorded on the digital disk (,). In reproduction, a RF signal in the wobble signal is converted into a digital signal by an A/D converter (,). The signal is demodulated by a demodulation circuit (,) for data output.

Digital disk recording and reproduction apparatus

Digital recording method, digital disk, digital disk recording device, and digital disk reproducing device

A digital modulator which inputs a data stream to convert to a channel bit stream. The multiplexed data block is generated by multiplexing dummy data to any position within each data block cut out of the data stream one by one. The first Reed-Solomon code is generated by Reed-Solomon-encoding the multiplexed data block as an information part. A plurality of second Reed-Solomon codes are generated by adding a plurality of Reed-Solomon codes for scrambling each of which has identification data showing its scrambling pattern in the same position as that of the dummy data, and the code length of information part and parity part is the same as the first Reed-Solomon code. The second Reed-Solomon code in which the characteristics becomes desirable after modulation among the plurality of the second Reed-Solomon codes is set for output.

Digital modulation and demodulation

A digital modulation circuit which minimizes a DC component of an NRZI modulated code sequence while setting the T.sub.max and T.sub.W not to be varied. An m-n coding mode is determined for each data block composed of the predetermined number of m-bit datawords. That is, an m-n coding mode which minimizes the absolute value of the DSV is selected and the selected m-n coding mode is utilized for the m-n coding of the current data block. The code indicating the selected m-n coding mode is multiplexed to the m-n coded current block. An m--m mapping table is also determined for each data block. That is, such an m--m mapping table that minimizes the absolute value of the DSV is selected and the selected m--m mapping table is utilized for the m--m translation of the current data block. Then, the m--m mapped data block is m-n translated into a code block composed of the same number of n-bit codewords by utilizing the single m-n translation table.

Digital modulation circuit and digital demodulation circuit

Several different types of look-up tables are available in the present invention. That is, one look-up table is selected for each m-bit dataword according to the number of consecutive 0's at lower digits, which include a lowermost digit, of the n-bit codeword preceding thereto and the encoding is performed by using the selected look-up table. Furthermore, the bit-pattern at the lower digits, which include a lowermost digit, of a current n-bit codeword is replaced according to the number of consecutive 0's at upper digits, which include an uppermost digit, of the n-bit codeword following thereafter.

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Tokyo, Japan

Akiomi Kunisa