Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Akio Uenishi

Katsumi Nakamura

Yasuaki Fukumochi

Hiroshi Yamaguchi

Tadaharu Minato

Fumitoshi Yamamoto

Mamoru Seo

Saori Uchida

A semiconductor device has a surge protection circuit electrically connected to a signal input terminal and including a diode and a transistor. The diode has its cathode region constituted of an ndiffusion layer, an nepitaxial layer, an n-type diffusion layer and an ndiffusion layer. The ndiffusion layer is electrically connected to a conductive layer and formed at a main surface of a semiconductor substrate. The ndiffusion layer constitutes, together with a p-type diffusion layer, a pn junction where Zener breakdown occurs, and the pn junction with the Zener breakdown occurring therein is distant from a field oxide film. Then, the semiconductor device with the surge protection circuit without suffering from current leakage and thus normally operating can be achieved.

Semiconductor device with surge protection circuit capable of preventing current leakage

A semiconductor device includes: a semiconductor substrate; a first insulating film formed on the semiconductor substrate; a polysilicon resistor film formed on the first insulating film; a second insulating film formed on the resistor film; a high heat conductor film consisting of a highly heat-conducting material formed on the second insulating film; and a pair of terminal wirings formed on the second insulating film and connected to the resistor film, in which a thickness Tof the second insulating film is thinner than a thickness Tof the resistor film.

Semiconductor device

The protecting element includes an NPN transistor having an emitter connected to an input/output terminal and a collector and a base connected to a ground terminal. The input/output terminal has the possibility of receiving a surge voltage. The input/output terminal, which may be referred to as a pad, is connected to a semiconductor integrated circuit IC to be protected against the surge voltage. The arrangement of the semiconductor integrated circuit IC is not limited to a specific one.

Semiconductor device serving as a protecting element

Isolation regions, a peripheral anode, an N-type island region for output and a passive N-type island region are formed at the main surface of a P substrate. A dummy N-type island region is formed at a region located between two isolation regions. A P-type region is formed at the surface of this N well. A pair of N type regions are formed at the surface of P-type region. A gate electrode is formed on a portion of P-type region interposed between N type regions. N type region is connected to ground while N type region is electrically connected to isolation region. Accordingly, current is restricted from flowing between the N-type island region for output and the passive N-type island region so as to obtain a semiconductor device in which occurrence of malfunctions is prevented.

Semiconductor device with structure restricting flow of unnecessary current therein

In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n,silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

Semiconductor device having high breakdown voltage and method of manufacturing the same

A power switching device which decreases both surge voltage and switching loss. As the inductor is connected to the emitter electrode of the IGBT element, the potential of the emitter electrode changes in the direction in which the IGBT element maintains the ON state with the attenuation of the main current when the IGBT element turns OFF from ON. Furthermore, as the inductor is included in the path of the OFF driving current for bringing the IGBT element to OFF, the OFF driving current once raises and then decreases. As a result, because the transition from ON to OFF calmly proceeds, the occurrence of the surge voltage is suppressed. On the other hand, since the inductor is not included in the path of the ON driving current, the transition from OFF to ON of the IGBT element is rapidly made. Accordingly, the switching loss occurring in the transition period is decreased. The decrease in the surge voltage and the decrease in the switching loss are compatibly realized.

Power switching device

In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n.sup.- silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

Semiconductor device having high breakdown voltage and method of

An n type diffusion region and a p type diffusion region are formed in a region sandwiched between trenches arranged at a first main surface of a semiconductor substrate. A p type well is formed in the n- and p-type diffusion regions nearer the first main surface. A source n.sup.+ diffusion region is formed at the first main surface within the p type well. A gate electrode layer is formed opposite to the p type well sandwiched between the n type diffusion region and the source n.sup.+ diffusion region with a gate insulating layer disposed therebetween. The n- and p-type diffusion regions each have an impurity concentration distribution diffused from a sidewall surface of a trench. Thus, a fine, micron-order pn repeat structure can be achieved with sufficient precision and a high breakdown voltage semiconductor device is thus obtained which has superior on-state voltage and breakdown voltage as well as fast switching characteristics.

Method for forming high breakdown semiconductor device

Internal gate electrodes (71) are all connected in common to a gate terminal, and a floating gate electrode (72) is connected to the gate electrode of an NMOS transistor (M1). An external emitter electrode (91) is provided on a first major surface of P-type diffused lease region (21), and N-type diffused emitter region (31) and P-type diffused base region (21) are short-circuited. The source of the NMOS transistor (M1) and an emitter terminal are also connected to the external emitter electrode (91). The drain of the NMOS transistor (M1) is connected to an external terminal.

Insulated gate type semiconductor device with potential detection gate

Trenched high breakdown voltage semiconductor device

In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n.sup.31 silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

A p type collector region is formed at the side of collector surface of an n.sup.- region with an n type buffer region. This p type collector region has a structure including a p type impurity region and a p.sup.+ impurity region. Impurity concentrations of the p type impurity region, the p.sup.30 impurity region and the n type buffer region are of a prescribed relationship, and the diffusion depth of the p type impurity region from the collector surface is not lower than 2.0 .mu.m. Thus, a semiconductor device in which turn-off loss is sufficiently low and which is not likely to be affected by thermal treatment upon formation of each of the impurity V regions can be obtained.

High breakdown voltage semiconductor device

A semiconductor device is formed from a thyristor and a MOSFET cascade-connected in which the thyristor includes a bipolar transistor cascade-connected with the MOSFET, the base (p semiconductor region) of which is adapted to be punched through by the application of a working voltage. Thus, the thyristor can easily be latched and unlatched in response to the turn-on and turn-off of the MOSFET. Thus the semiconductor device can be securely on/off controlled by only the single gate (G) of the MOSFET. By using such semiconductor device as a switching element in a flash control device, a high performance flash control device with high flashing efficiency is provided.

Method of fabricating a flash control device which uses

A semiconductor device comprises a first conductivity type semiconductor layer and a second conductivity type well region which is formed on the semiconductor layer. The well region includes a first semiconductor region of a first depth and a second semiconductor region of a second depth deeper than the first depth which is provided in the central portion of the first semiconductor region. The ratio of the first depth to the second depth is settled in a range from 0.85 to 0.95 in order to increase the breakdown voltage of the semiconductor device.

Semiconductor device and method of fabricating the same

The semiconductor device is composed of a thyristor and a MOSFET cascade-connected. The thyristor includes a bipolar transistor cascade-connected with the MOSFET, the base (p.sup.-- semiconductor region) of which is adapted to be punched through by the application of a working voltage. Thus, the thyristor can easily be latched and unlatched in response to the turn-on and turn-off of the MOSFET. Thus the semiconductor device can be securely on/off controlled by only the single gate (G) of the MOSFET. By using such semiconductor device as a switching element in a flash control device, a high performance flash control device with high flashing efficiency is provided.

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Hyogo, Japan

Akio Uenishi