Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Akio Toda

Junichi Fujikata

Jun Ushida

Motofumi Saitoh

Shinji Fujieda

Haruihiko Ono

Ryota Yuge

Kohji Kanamori

Junichi Suzuki

Noriaki Kodama

Masayuki Terai

Teiichirou Nishizaka

Kimiyoshi Fukatsu

Yasuhide Den

The present invention relates to a negative electrode material for secondary batteries, comprising graphite; wherein

Negative electrode material for secondary battery, and secondary battery

A downsized, low-power electro-optical modulator that achieves reducing both of the additional resistance in the modulation portion and the optical loss each caused by electrodes at the same time is provided. The electro-optical modulator includes a rib waveguide formed by stacking a second semiconductor layerhaving a different conductivity type from a first semiconductor layeron the first semiconductor layervia a dielectric film, and the semiconductor layersandare connectable to an external terminal via highly-doped portionsand, respectively. In a region in the vicinity of contact surfaces of the semiconductor layersandwith the dielectric film, a free carrier is accumulated, removed, or inverted by an electrical signal from the external terminal, and whereby a concentration of the free carrier in an electric field region of an optical signal is modulated, so that a phase of the optical signal can be modulated. At least one of the semiconductor layersandis wider than the stacked portion. At least one of the highly-doped portionsandis formed outside the stacked portion.

Electro-optical modulator

To provide an optical modulator having a reduced size and reduced power consumption and capable of being easily connected to a waveguide and a method of manufacturing the optical modulator. The optical modulator has at least semiconductor layer () having a rib-shaped portion and doped so as to be of a first conduction type, dielectric layer () laid on first-conduction-type semiconductor layer (), and semiconductor layer () laid on dielectric layer (), having the width at the side opposite from dielectric layer () increased relative to the width of the rib-shaped portion, and doped so as to be of a second conduction type.

Optical modulator

An optical modulation structure includes a lower cladding layer (), a first silicon layer () integrally formed from silicon of a first conductivity type on the lower cladding layer () while including a core () and slab regions () arranged on both sides of the core () and connected to the core, a concave portion () formed in an upper surface of the core (), and a second silicon layer () of a second conductivity type formed on a dielectric layer () in the concave portion () so as to fill the concave portion ().

Optical modulation structure and optical modulator

A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap.

Semiconductor device, and its manufacturing method

A MOS semiconductor device isolated by a trench device isolation region includes a p-channel MOS field effect transistor having a source/drain region with a length in the channel direction that is not more than 1 micrometer, and a gate length that is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the sourced/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film including the silicon oxide film only.

MOS semiconductor device isolated by a device isolation film

While using conventional manufacturing processes, it is intended to apply a compressive strain in the channel direction to the p-channel MOS field effect transistor and also apply a tensile strain in the channel direction to the n-channel MOS field effect transistor for increasing both MOS currents. In the MOS semiconductor device isolated by a trench device isolation regions, the p-channel MOS field effect transistor is designed so that a length of a source/drain region in the channel direction is not more than 1 micrometer, and the gate length is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the source/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film including the silicon oxide film only.

MOS semiconductor device

A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

Growing community of inventors

Tokyo, Japan

Akio Toda