Kabushiki Kaisha Toshiba

Kogakuin University

Akio Takano

Yoshitaka Hokomoto

Takahiro Kawano

Bungo Tanaka

Tetsuo Sakamoto

Haruko Akutsu

Hirobumi Matsuki

Reiko Saito

According to one embodiment, a mass spectrometer includes a sample stage provided to hold a sample; an analysis unit disposed to face a sample placement surface of the sample table, and performing mass analysis; an ion beam source provided to irradiate an ion beam toward the sample placement surface; an assist energy source supplying assist energy to a target area between the sample placement surface and the analysis unit; and a laser light source irradiating the target area with laser light.

Mass spectrometer and mass spectrometry method

A semiconductor device according to an embodiment of the present invention has a transistor section which includes a trench gate type transistor, and a gate line section which includes a part provided between transistor sections. The device includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a base layer formed in the semiconductor layer, and provided with trenches in the transistor section and the gate line section, the trenches in the transistor section extending in a first direction parallel to a direction in which the transistor extends, the trenches in the bit line section extending in a second direction perpendicular to the first direction, and the trenches in the transistor section penetrating the base layer to reach the semiconductor layer, a source layer formed in the semiconductor layer in the transistor section, the source layer being located on the base layer, a gate insulator formed on surfaces of the base layer and the semiconductor layer exposed to the trenches in the transistor section and the gate line section, and on an upper surface of the base layer between the trenches in the gate line section, a gate line layer formed on the gate insulator, and including a part buried in the trenches in the transistor section, an inter layer dielectric formed on the gate line layer, and a source line layer formed on the inter layer dielectric, and electrically connected to the source layer in the transistor section.

Semiconductor device and method of manufacturing the same

A semiconductor device comprises a semiconductor substrate having an upper surface and a lower surface. A semiconductor layer is formed on the upper surface of the semiconductor substrate. A base region of a first conduction type is formed in the semiconductor layer. A source region of a second conduction type is formed in the base region. A drain region of the second conduction type is formed apart from the source region in the semiconductor layer. A gate electrode is formed on a gate insulator above the semiconductor layer between the source region and the drain region. A first interlayer insulator is formed on the semiconductor layer to cover the gate electrode. A short electrode is formed to short the base region and the source region. A second interlayer insulator is formed to cover the first interlayer insulator and the short electrode. A drain electrode is formed over the second interlayer insulator and connected to the drain region with the use of a contact hole formed through the first and second interlayer insulators. A source electrode is formed on the lower surface of the semiconductor substrate. The short electrode extends over the first interlayer insulator from the source region toward the drain region. A side of the short electrode at least coincides with a side of the gate electrode located toward the drain region with respect to positions in a direction defined as directing from the source region toward the drain region.

Semiconductor device

In a semiconductor layer of the first conductivity type, a first diffusion region of the second conductivity type is formed which includes a low resistance layer and a high resistance layer. This semiconductor layer of the first conductivity type has its thickness that is less than or equal to the lateral width of the high resistance layer.

A semiconductor device comprising a semiconductor substrate having first and second surfaces opposing each other, the substrate including a plurality of cells sharing a common drain region, each of the cells having source and gate regions, a surface source electrode connected to the source region of each of the cells and provided on the first surface, a strap member coupled with the surface source electrode by ultrasonic waves, a gate polysilicon wiring layer connecting the gate region of each of the cells and having a silicide layer in at least a portion of a surface thereof, a surface gate electrode connected to the gate polysilicon wiring layer and provided on the first surface, and a drain electrode provided on the second surface and shared by the cells.

Silicided trench gate power mosfets ultrasonically bonded to a surface source electrode

A trench gate type semiconductor device includes a first semiconductor layer having first and second main surfaces, a second semiconductor layer of a first conductivity type as formed on the first main surface of the first semiconductor layer, a third semiconductor layer of a second conductivity type as formed on the second semiconductor layer, a fourth semiconductor layer of the first conductivity type as formed at a surface of the third semiconductor layer, a gate electrode having a polycrystalline silicon layer being buried in a trench formed to a depth reaching the second semiconductor layer from a surface of the fourth semiconductor layer with a gate insulating film interposed therebetween and having an upper end portion protruding upwardly from a trench upper end opening while having its width greater than a width of the trench and a metal silicide film formed at an upper surface and side surfaces of the upper end portion of the polycrystalline silicon layer, a first main electrode in contact with both the fourth third semiconductor layer, and a second main electrode formed at the second main surface of the first semiconductor layer.

Growing community of inventors

Kawasaki, Japan

Akio Takano