Fuji Electric Co., Ltd.

Fuji Electric Systems Co. Ltd.

Fuji Electric Holdings Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Akio Sugi

Naoto Fujishima

Mutsumi Kitamura

Katsuya Tabuchi

Manabu Takei

Noriyuki Iwamuro

Haruo Nakazawa

Koh Yoshikawa

Yasuhiko Onishi

Shinichiro Matsunaga

Setsuko Wakimoto

Kouta Takahashi

C Andre T Salama

Hong-fei Lu

Tatsuji Nagaoka

A semiconductor apparatus that has a first parallel pn-layer formed between an active region and an n-drain region. A peripheral region is provided with a second parallel pn-layer, which has a repetition pitch narrower than the repetition pitch of the first parallel pn-layer. An n-surface region is formed between the second parallel pn-layer and a first main surface. On the first main surface side of the n-surface region, a plurality of p-guard ring regions are formed to be separated from each other. A field plate electrode is connected electrically to the outermost p-guard ring region among the p-guard ring regions. A channel stopper electrode is connected electrically to an outermost peripheral p-region of the peripheral region.

Semiconductor apparatus

A parallel p-n layer () is provided as a drift layer between an active portion and an ndrain region (). The parallel p-n layer () is formed by an n-type region () and a p-type region () being repeatedly alternately joined. An n-type high concentration region () is provided on a first main surface side of the n-type region (). The n-type high concentration region () has an impurity concentration higher than that of an n-type low concentration region () provided on a second main surface side of the n-type region (). The n-type high concentration region () has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (). Also, the n-type high concentration region () has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region () adjacent to the p-type region ().

Superjunction semiconductor device with reduced switching loss

A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.

Semiconductor device, battery protection circuit and battery pack

A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

Semiconductor device and manufacturing method of the semiconductor device

In a MIS-type semiconductor device having a trench gate structure, a withstand voltage is ensured without changing the thickness of a drift layer and on-resistance can be reduced without applying a high gate drive voltage. The lower half of a trench extending through a p-base region into an n-drift region is filled with a high-permittivity dielectric having a relative permittivity that is higher than that of a silicon oxide film, preferably a silicon nitride film, and an insulated gate structure including a gate insulator and a gate electrode is fabricated on the high-permittivity dielectric. The depth dof the deepest portion of the high-permittivity dielectric is designed to be deeper than the depth dof a depletion layer in the semiconductor region away from the high-permittivity dielectric.

Semiconductor device and method for manufacturing the same

Gate electrodes of a TLPM and gate electrodes of planar devices are formed by patterning a same polysilicon layer. Drain electrode(s) and source electrode(s) of the TLPM and drain electrodes and source electrodes of the planar devices are formed by patterning a same metal layer. Therefore, the TLPM and the planar devices can be connected electrically to each other by resulting metal wiring layers and polysilicon layers without the need for performing wire bonding on a printed circuit board.

Semiconductor device with integrated trench lateral power MOSFETs and planar devices

A semiconductor device is provided that can be manufactured by a simpler process than a conventional lateral trench power MOSFET for use with an 80V breakdown voltage, and which has a lower device pitch and lower on-state resistance per unit area than a conventional lateral power MOSFET for use with a lower breakdown voltage than 80V. A gate oxide film is formed thinly along the lateral surfaces of a trench at a uniform thickness. Then, a gate oxide film is formed along the bottom surface of the trench by selective oxidation so as to be thicker than the gate oxide film on the lateral surfaces of the trench and so as to become progressively thicker from the edge of the bottom surface of the trench toward drain polysilicon.

Trench lateral power MOSFET and a method of manufacturing the same

A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and a high operation speed in a semiconductor device provided with a lateral IGBT, and that prevents malfunctions such as latchup when IGBTs or an IGBT and CMOS devices are integrated together. The structure includes an SOI substrate having a supporting substrate, an oxide film and a p-semiconductor layer. An island-like element-forming region is isolated by a trench isolation region from surroundings. The trench isolation region includes an isolation trench with an insulation film on its inner wall. The device trench is formed in the element-forming region. A gate electrode is formed with a gate insulator film in the device trench. A collector region and an emitter region outside are provided respectively on the bottom and the outside of the device trench.

Semiconductor device

To reduce the on-resistance in a semiconductor device, such as a trench lateral power MOSFET, a trench etching region forms a mesh pattern in which a first trench section, formed in an active region, and a second trench section, formed in a gate region for leading out gate polysilicon to a substrate surface, intersect each other. An island-like non-trench region, which is left without being subjected to etching, is divided into a plurality of smaller regions by one or more third trench section that connect with the first and second trench sections that form the mesh pattern. In each non-trench region, a contact section for connecting a drain region (or a source region) and an electrode is formed so as to be spread over all of the smaller regions in the non-trench region.

Semiconductor device and method of manufacturing the device

A trench-type lateral power MOSFET is manufactured by forming an n-type diffusion region, which will be a drift region, on a p-type substrate; selectively removing a part of substrate and a part of n-type diffusion region to form trenches; forming a gate oxide film of 0.05 &#x3bc;m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p-type base region and an n-type diffusion region, which will be a source region, in the bottom of each trench; and forming an n-type diffusion region, which will be a drain region, in the surface portion of n-type diffusion region. The MOSFET has reduced device pitch, a reduced on-resistance per unit area and a simplified manufacturing process.

Trench-type MOSFET having a reduced device pitch and on-resistance

Semiconductor device and its manufacturing method

A trench-type lateral power MOSFET is manufactured by forming an n -type diffusion region, which will be a drift region, on a p -type substrate; selectively removing a part of substrate and a part of n -type diffusion region to form trenches; forming a gate oxide film of 0.05 &mgr;m in thickness in each trench; forming a polycrystalline silicon gate layer on gate oxide film; forming a p -type base region and an n -type diffusion region, which will be a source region, in the bottom of each trench; and forming an n -type diffusion region, which will be a drain region, in the surface portion of n -type diffusion region. The MOSFET has reduced device pitch, a reduced on-resistance per unit area and a simplified manufacturing process.

Growing community of inventors

Nagano, Japan

Akio Sugi