Kioxia Corporation

Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Akio Sugahara

Yoshikazu Harada

Yuji Nagai

Masahiro Yoshihara

Junichi Sato

Shoichiro Hashimoto

Masanobu Shirakawa

Masaru Koyanagi

Naomi Takeda

Noriyasu Kumazaki

Akihiro Imamoto

Takehisa Kurosawa

Kazuto Uehara

Yuri Terada

Naofumi Abiko

Yoshikazu Takeyama

Masashi Yamaoka

Yuzuru Shibazaki

Norichika Asaoka

Takaya Handa

Bushnaq Sanad

Zhao Lu

Ryosuke Isomura

Toshifumi Watanabe

Mami Kakoi

Kohei Masuda

Mitsuaki Honma

Yasuhiro Hirashima

Mitsuhiro Abe

Hisashi Fujikawa

Kenta Shibasaki

Yoshihiko Shindo

Naoya Tokiwa

Toshio Yamamura

Dai Nakamura

Takahiro Shimizu

Masaki Fujiu

Shigeki Nagasaka

Yousuke Hagiwara

Daisuke Arizono

Yuko Utsunomiya

Yasufumi Kajiyama

Hayao Kasai

Osamu Nagao

Zhao Lyu

A memory system includes a memory device and a memory controller. The memory device includes a memory cell array configured to store data, a data input and output interface configured to receive a command, an address, and data to be written into the memory cell array from the memory controller, and to output data read from the memory cell array to the memory controller, and a control circuit configured to control the memory cell array to perform an operation in response to receipt of a command while a first control signal is being asserted by the memory controller and receipt of an address subsequent to the command while a second control signal is being asserted by the memory controller.

Memory device

A memory system according to an embodiment includes: a first chip including a first plane and a first input/output circuit; and a controller which is capable of issuing a command for controlling the first chip. The first plane includes: a first memory cell array having a plurality of first memory cell transistors; and a first latch circuit which is capable of storing first read data read from the first memory cell array. The first input/output circuit includes a first FIFO circuit which is capable of fetching the first read data from the first latch circuit. The controller is capable of transmitting to the first chip a first command for ordering fetching of the first read data from the first latch circuit to the first FIFO circuit during a period in which a read operation is executed on the first plane.

Memory system which orders data fetching from a latch circuit during execution of a read operation

According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.

Memory system and memory device

According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.

Semiconductor memory device and memory system

A semiconductor memory device according to an embodiment includes a first storage circuit. The first storage circuit is configured to store a first unique number uniquely assigned, and a first chip address having a bit number smaller than that of the first unique number and used to identify the semiconductor memory device from other semiconductor memory devices.

A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.

Semiconductor memory device

A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.

A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

Memory system

A semiconductor memory device according to an embodiment includes a plurality of planes each including a plurality of blocks each including a memory cell, an input/output circuit configured to receive a command set from an external controller, and a sequencer configured to execute an operation in response to the command set. Upon receiving a first command set that instructs execution of a first operation, the sequencer executes the first operation. Upon receiving a second command set that instructs execution of a second operation during execution of the first operation, the sequencer executes the second operation in parallel with the first operation. Upon receiving a third command set that instructs execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.

A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

Memory device which generates operation voltages in parallel with reception of an address

A memory system includes a memory controller and a semiconductor storage device including a power supply pad, first, second, third, and fourth signal pads to which first, second, third, and fourth signals are respectively input, a memory cell array, a data register, and a control circuit executing an operation to output data stored in the data register through the fourth signal pad. The memory controller performs a mode setting operation by toggling the third signal input, after at least the first or second signal has been switched at a first timing after supplying power to the power supply pad, perform an initial setting operation by transmitting a power-on read command at a second timing after the first timing, and transmit a data-out command, at a third timing after the second timing. The semiconductor storage device receives the power-on read and data-out commands via the first and second signal pads.

A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Semiconductor storage device and method of controlling the same

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Yokohama Kanagawa, Japan

Akio Sugahara