Matsushita Electric Industrial Co., Ltd.

Akio Shimano

Tatsuo Otsuki

Hiromitsu Takagi

Ikuko Aoki

Shutaro Nambu

Hiromitsu Aoki

Shin Katsu

An FET circuit suitable for a latch has a pair of inverters. The input stage FET of each of the inverters is connected such that the gate electrode thereof is connected to receive an output signal of the FET of the other inverter through a circuit having an FET and at least a diode. The sources of the input stage FETs are connected to a common connection point, and a current source arrangement such as a resistor is connected between the common connection point and a power supply terminal. The circuit provides an extended allowable range of the effective threshold voltage V.sub.T and has small power consumption.

Mesfet latch circuit

A buffered FET logic gate circuit has a bias diode (9), which is connected across the gate and the source of a current source FET (4) of a buffer part (3, 4), and a capacitor (8), which is connected across the gate of said FET (4) and an input terminal (V.sub.I); and thereby a high load drivability with a low power consumption rate is realized.

Buffered FET logic gate using depletion-mode MESFET's.

An epitaxial layer having a specified conductivity type formed on a semiinsulative or high resistivity semiconductor substrate or insulative substrate is anodized (anodically oxidized) by a predetermined D.C. current under an illumination of light of a predetermined intensity, thereby a depletion layer is formed beneath an oxide layer, which is formed by the anodizing, and the anodizing ceases in areas where the bottom face of the depletion layer reaches the semiinsulative or high resistivity semiconductor substrate or insulative substrate thus retaining a layer of highly uniform thickness layer of the epitaxial grown layer on the substrate.

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Osaka, Japan

Akio Shimano