Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Hitachi, Ltd.

Other

Akio Nishida

Hiraku Chakihara

Masaru Nakamichi

Koichiro Ishibashi

Kenichi Osada

Yoshikazu Saitoh

Naoki Kitai

Mitsuhiro Noguchi

Kousuke Okuyama

Masahiro Moniwa

Yasuko Yoshida

Toshiaki Yamanaka

Shinichiro Kimura

Makoto Mizuno

Keiji Okamoto

Tadanori Yoshida

Yasuhiko Takahshi

Hideyuki Matsuoka

Masahiro Tadokoro

Kota Funayama

Naonori Wada

Shuji Ikeda

Eiichi Murakami

Riichiro Takemura

Tomonori Sekiguchi

Norio Suzuki

Natsuki Yokoyama

Norikatsu Takaura

Osamu Tsuchiya

Shigeru Shiratake

Atsushi Ogishima

Kikuo Kusukawa

Hisakazu Otoi

Yasuaki Yonemochi

Yoshiyuki Kawashima

Kazuhiro Komori

Jiro Yugami

Koichi Toba

Kiyokazu Nakagawa

Kazunori Umeda

Koichi Imato

Noriyuki Yabuoshi

Sousuke Tsuji

Hideo Miwa

Mitsuhiro Higuchi

Toshiyuki Mine

Kenichi Kuroda

Masataka Minami

Naoki Yamamoto

Masao Inoue

Jun Shibata

Toshikazu Shimada

Shiro Kamohara

Kazuhito Ichinose

Tsuyoshi Koga

Yorinobu Kunimune

Hiroshi Tobimatsu

Kazuhito Matsukawa

Yoshiki Maruyama

Yoshiko Higashide

Nobuto Nakanishi

Kyoko Umeda

Akira Fujimoto

The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Semiconductor integrated circuit device with reduced leakage current

To control a grain growth on laminated polysilicon films, a method of manufacturing a semiconductor device is provided. The method includes: forming a first polysilicon film () on a substrate (); forming an interlayer oxide layer () on a surface of the first polysilicon film (); forming a second polysilicon film () in contact with the interlayer oxide layer () above the first polysilicon film (); and performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in a gas atmosphere containing nitrogen, after formation of the second polysilicon film ().

Semiconductor device and manufacturing method thereof

To provide a semiconductor device having improved reliability. A semiconductor device is provided forming a control gate electrode for memory cell on a semiconductor substrate via a first insulating film; forming a memory gate electrode for memory cell, which is adjacent to the control gate electrode, on the semiconductor substrate via a second insulating film having a charge storage portion; forming ntype semiconductor regions for source or drain in the semiconductor substrate by ion implantation; forming sidewall spacers on the side wall of the control gate electrode and the memory gate electrode; forming ntype semiconductor regions for source or drain in the semiconductor substrate by ion implantation; and removing an upper portion of the second insulating film present between the control gate electrode and the memory gate electrode. A removal length of the second insulating film is larger than the depth of the ntype semiconductor regions.

Method of manufacturing semiconductor device

The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, in a memory cell region, a control gate electrode formed of a first conductive film is formed over the main surface of a semiconductor substrate. Then, an insulation film and a second conductive film are formed in such a manner as to cover the control gate electrode, and the second conductive film is etched back. As a result, the second conductive film is left over the sidewall of the control gate electrode via the insulation film, thereby to form a memory gate electrode. Then, in a peripheral circuit region, a p type well is formed in the main surface of the semiconductor substrate. A third conductive film is formed over the p type well. Then, a gate electrode formed of the third conductive film is formed.

Method for manufacturing a semiconductor device

A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed.

Method of manufacturing nonvolatile semiconductor device

Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device

In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.

Method of manufacturing a semiconductor integrated circuit device

Growing community of inventors

Tachikawa, Japan

Akio Nishida