Kabushiki Kaisha Toshiba

Fuji Electric Co., Ltd.

Canon Kabushiki Kaisha

Denso Corporation

Mitsumi Electric Company Ltd.

Tokyo Shibaura Electric Co., Ltd.

Akio Nakagawa

Yoshihiro Yamaguchi

Yusuke Kawaguchi

Tomoko Matsudai

Norio Yasuhara

Kazutoshi Nakamura

Kiminori Watanabe

Ichiro Omura

Tsuneo Ogura

Hideyuki Funaki

Syotaro Ono

Hiromichi Ohashi

Mitsuhiko Kitagawa

Takashi Shinohe

Thuneo Thukakoshi

Toshiyuki Naka

Toru Takayama

Kazuyoshi Furukawa

Kazuya Nakayama

Yuki Kamata

Shinichi Hodama

Yoshinobu Sano

Hisashi Ishikawa

Kenichi Matsushita

Katsujiro Tanzawa

Yuichi Onozawa

Norihito Tokura

Tomoki Inoue

Masakazu Yamaguchi

Minami Takeuchi

Yusuke Kobayashi

Manabu Takei

Shigeki Takahashi

Takaki Tsutsui

Youichi Ashida

Kozo Kinoshita

Fumito Suzuki

Takashi Sato

Hiroshi Iwai

Tatsuya Yamada

Shin Nakamura

Kazuo Shimokawa

Toshihiko Iinuma

Masaki Toyoshima

Hirofumi Nagano

Satoshi Shiraki

Hiroomi Nakajima

Kouhei Morizuka

Noriaki Yoshikawa

Yosuke Sakurai

Hidetaka Hattori

Yasuhito Saito

Yasuhiro Katsumata

Shigeru Hasegawa

Tsutomu Kojima

Kaoru Imamura

Yoshiki Endo

Tadahide Hoshi

Katsuhiko Takigami

Osamu Usuda

Takashi Koyanagawa

Hiroshi Takei

Masahiro Urase

Haruki Arai

Morio Takahashi

Kazumi Inou

Tetsuzo Nakazawa

Keizo Hirayama

Ryo Sato

Masako Ooishi

Taiki Miura

Tomohiro Kawano

Tadashi Sakai

Naoharu Sugiyama

Yoshiro Baba

Masahiro Yamamoto

Yutaka Koshino

Yoshihiro Ikura

Chihiro Okado

Masaki Atsuta

Akira Yamada

Masayuki Sekimura

Takashi Satou

Tomokazu Domon

Miwako Akiyama

Ryoko Mise

Makoto Azuma

Masaru Shimbo

Eri Ogawa

Takao Yamamoto

Kiyoshi Fukuda

Hiroyasu Kudo

Hisato Kato

Tetsuzou Nakazawa

Yoshie Suzuki

Ken'ichi Matsushita

Kastsujino Tanzawa

Isuneo Ogura

Atsusi Kurobe

Yoshinori Terazaki

Provided is a semiconductor device including a drift region having a first conductivity type provided on a semiconductor substrate; a plurality of trench portions provided above the drift region, on a top surface side of the semiconductor substrate; a base region having a second conductivity type provided in a mesa portion sandwiched between the plurality of trench portions, in the semiconductor substrate; an emitter region having the first conductivity type provided above the base region, on a top surface of the mesa portion; and a contact region having the second conductivity type and a higher doping concentration than the base region, provided adjacent to the emitter region on the top surface of the mesa portion, wherein a mesa width of the mesa portion is less than or equal to 100 nm, and a bottom end of the contact region is shallower than a bottom end of the emitter region.

Semiconductor device

The present invention provides a semiconductor device including (a) a drift region of a first-conductivity-type, (b) a base region of a second-conductivity-type, (c) a plurality of trench portions arranged next to each other in a predetermined arrangement direction on the upper surface of the semiconductor substrate, (d) an emitter region of a first-conductivity-type which has a higher doping concentration than the drift region, (e) an accumulation region of a first-conductivity-type which has a higher doping concentration than the drift region, and (f) a second-conductivity-type region of a second-conductivity-type which has a higher doping concentration than the base region, wherein the accumulation region and the second-conductivity-type region are provided between the base region and the drift region in a non-channel mesa portion that does not have the emitter region provided therein and that is of mesa portions between adjacent ones of the plurality of trench portions.

A semiconductor device having a trench gate structure is provided. A semiconductor device is provided, including: a first-conductivity-type drift region provided in a semiconductor substrate; a first-conductivity-type accumulation region provided above the drift region and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region; and an electric-field relaxation layer provided between the accumulation region and the base region and having a lower doping concentration than the accumulation region. The electric-field relaxation layer may include a first-conductivity-type region including a region having a same doping concentration as the drift region.

In mesa regions between adjacent trenches disposed in an n-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.

Method of manufacturing a semiconductor device having two types of gate electrodes

For enhancing a reverse-recovery immunity of a diode element, a semiconductor device includes a first conductivity-type drift layer, a second conductivity-type anode region provided in an upper portion of the drift layer, an insulating film provided on the drift layer, an anode electrode having an ohmic contact portion ohmically contacted to the anode region through a contact hole penetrating the insulating film, and a Schottky electrode Schottky-contacted to a peripheral portion of the anode region.

Semiconductor device having schottky electrode connected to anode region

Semiconductor device having first and second gate electrodes

A semiconductor device has a reduced an on-voltage and uses a gate resistance to improve the trade-off relationship between turn-on loss Eon and dV/dt, and turn-on dV/dt controllability. A floating p-type region is provided in an n-type drift layer so as to be spaced from a p-type base region configuring a MOS gate structure. An emitter electrode and the floating p-type region are electrically connected by an n-type region provided in the surface layer of a substrate front surface. The n-type region is covered with a second insulating film which film is covered with an emitter electrode. By an electric field being generated in the n-type region by the emitter electrode provided on the top of the n-type region via the second interlayer insulating film, the n-type region forms a current path which causes holes accumulated in the floating p-type region to flow to the emitter electrode when turning on.

An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.

Information processing apparatus, information processing method, and storage medium

A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.

Lateral insulated gate bipolar transistor

A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

A data processing apparatus includes: a plurality of processing units adapted to process data according to input operation clocks; and a control unit adapted to measure response times of the plurality of processing units when the operation clocks of a common frequency are supplied to the plurality of processing units, and to control a frequency of the operation clocks to be supplied to at least one of the plurality of processing units so that a plurality of measured response times become closer to each other.

Data processing apparatus and control method for controlling clock frequency based on calculated frequency-to-response-time ratios

A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.

Current sensor, inverter circuit, and semiconductor device having the same

A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.

Semiconductor device having lateral diode

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Hiratsuka, Japan

Akio Nakagawa