Fujitsu Corporation

Akio Matsuda

Ryosuke Oishi

Koichiro Takayama

Tsuneo Nakata

Rafael Kazumiti Morizawa

Qiang Zhu

Ryousuke Oishi

Quang Zhu

Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step; converting the activity diagram to a second use case diagram representing a function of the object, based on the structure analyzed at the analyzing; verifying uniformity of the first use case diagram and the second use case diagram; and outputting a verification result obtained at the verifying uniformity.

Computer product for supporting design and verification of integrated circuit

An information processing apparatus includes a first detector that detects a scheduled starting time of an event to be corrected and executed at the current time or thereafter; a second detector that detects in processing contents differing from that of the event detected by the first detector, a scheduled starting time of each event to be executed at the current time or thereafter; a calculator that calculates the difference between the scheduled starting time detected by the first detector and each scheduled starting time detected by the second detector; a determiner that determines a target event for the event to be corrected, based on the calculated differences; and a corrector that corrects the scheduled starting time of the event to be corrected such that an interval becomes short between the scheduled starting time of the event to be corrected and the scheduled starting time of the target event.

Information processing apparatus, power control method, and computer product

A non-transitory, recording medium stores therein a program that causes a computer to execute extracting from hardware description of a circuit, a conditional branch statement representing a conditional branch process; determining whether the extracted conditional branch statement includes at least three condition expressions, where a given combination thereof has exclusive satisfying conditions; extracting from the conditional branch statement determined at the determining, a combination of condition expressions for which satisfying conditions are exclusive; extracting each condition expression from the extracted combination and creating, for each extracted condition expression and according to an order of appearance in the hardware description, a conditional branch statement in which the extracted condition expression has a hierarchical relationship with a condition expression not included in the combination; generating an assertion for checking whether a specified condition is satisfied in each created conditional branch statement; and outputting, as assertion data of the circuit, the generated assertion.

Verification support apparatus and verification support method to verify target circuit based on hardware description information

A verification support apparatus includes an identifying unit that, by using a pre-change specification and a post-change specification given before and after a specification change in a subject to be verified, identifies an area that has changed from among a plurality of specification items included in the post-change specification and a selecting unit that selects a specification item from among the areas identified by the identifying unit. The verification support apparatus further includes a searching unit that, by referring a transition graph concerning the specification items included in the post-change specification and by tracing specification items as origins of transitions from a starting point that is the specification item selected by the selecting unit, searches for a route made up of specification items affected by the specification change; and an output unit that outputs a search result of the searching unit.

Verification support apparatus, verification support method, and computer product

A verification target register to be verified is specified from a configuration of a verification target circuit, and patterns requiring verification are extracted as a coverage standard with regard to the specified verification target register. When the patterns are extracted, a DIRW matrix is prepared to indicate possibly occurring state transitions among four states Declare, Initialize, Read, and Write in the register included in the verification target circuit, and used to decide two coverage standards, a matrix coverage standard and an implementation coverage standard.

Verification supporting system

A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a combinational circuit to be verified; extracting, from the hardware description, a conditional branch description expressing conditional branch processing; identifying, from among conditional branch descriptions extracted at the extracting of a conditional branch description and based on a description sequence in the hardware description, a combination of conditional branch descriptions having a hierarchical relation; extracting, from among combinations of conditional branch descriptions identified at the identifying, a combination having a potential to satisfy a specified condition; creating a simulation program that causes the specified condition for the conditional branch descriptions included in the combination extracted at the extracting of the combination to be satisfied; and outputting, as assertion information of the combinational circuit, the simulation program created for each combination at the creating.

Hardware logic verification support apparatus, verification support method and computer product

A computer-readable recording medium stores therein a verification support program that causes a computer to execute receiving a hardware description of a sequential circuit to be verified and a timing specification that indicates a timing constraint in the hardware description; converting the hardware description into a control flow graph that expresses a flow of control in the sequential circuit; indentifying, from the control flow graph and as a combination of conditional branch descriptions having a hierarchical relation, conditional branch descriptions that are connected in parallel; extracting, from among identified combinations of conditional branch descriptions, a combination having a potential to satisfy specified conditions; creating a simulation program that, at a timing satisfying the timing specification, causes the conditional branch descriptions included in the extracted combination to satisfy the specified conditions; and outputting, as assertion information of the sequential circuit, the simulation program created at the creating.

In a verification supporting apparatus, a recording unit records a DIRW matrix in which a state transition possibly occurring in a register of a circuit to be verified and information concerning validity of a path corresponding to the state transition are set and an acquiring unit acquires a control data flow graph that includes a control flow graph having a data flow graph written therein. When a register is designated for verification, a data flow graph having described therein the designated register is extracted from the control data flow graph. From the data flow graph extracted, a path indicating the flow of data concerning the register is extracted. The state transition of the path extracted is identified and if the state transition is determined to be is set in the DIRW matrix, information concerning the validity set in the DIRW matrix and the path are correlated, and output.

Verification supporting apparatus, verification supporting method, and computer product

A method of generating a scenario includes generating a specification model by describing a specification in a predetermined descriptive language, extracting a plurality of operations from the specification model, generating a plurality of operation descriptions, each of which corresponds to one of the operations and includes an operation name and a constraint condition, generating at least one cause-effect graph that combines the operations based on the operation descriptions, and extracting as a scenario a series of operations from the cause-effect graph.

Systematic generation of scenarios from specification sheet

A verification support apparatus that verifies operation of a circuit includes a receiving unit, a detecting unit, and a determining unit. The receiving unit receives implementation description data of the circuit. Based on the implementation description data, the detecting unit detects a functional block that is in the circuit and includes an external input terminal that receives an external input signal. Based on a detection result of the detecting unit, the determining unit determines the functional block to verify an abnormal-event operation. The abnormal-event operation is an operation that differs from an operation implementing a function of the circuit.

Verification support method and apparatus, and computer product

A relationship acquisition unit acquires the relationship between a plurality of sequences to be implemented to realize the functions required for a system to be designed and an object to and from which the sequences deliver and receive messages. A grouping unit groups the sequences which deliver and receive messages to and from the same object to make a group of sequences associated with the object. A duplication dissolution unit dissolves, when the same sequence belongs to different groups of sequences in duplication, the duplication of the sequence based on the relationship, between the sequence and other sequences which deliver and receive messages to and from the object to and from which the sequence delivers and receives messages, of the implementation order of the object. An output unit associates each group and outputs the sequences belonging to the group of sequences associated with the functional blocks.

Growing community of inventors

Kawasaki, Japan

Akio Matsuda