Sanyo Electric Co., Ltd.

Tottori Sanyo Electric Co., Ltd.

Akio Kosaka

Toshinori Iinuma

Mitsufumi Yoshimoto

Mitsuji Hama

Masahiro Narita

Takashi Kawakami

Hama: Mitsuji

A baseband signal generator according to the present invention performs differential encoding and mapping processings for a digital baseband signal and limits bandwidths of the obtained symbol mapping data of an I phase and a Q phase by digital filters. Each digital filter includes a circuit for accumulating symbol mapping data corresponding to a plurality of symbol sections, a plurality of ROMs provided corresponding to the plurality of symbol sections for storing symbol data corresponding to a predetermined filter waveform, and an adder for adding symbol data output from there ROMs. The adder outputs a digital baseband signal whose bandwidth is limited, which signal is converted into an analog baseband signal by a D/A converter and supplied to an analog modulation unit.

Baseband signal generator for digital modulator

A digital DQPSK modulator according to the present: invention limits respective bands of symbol mapping data of I phase and Q phase obtained by applying differential encoding and mapping processings to a digital baseband signal, and multiplies the obtained data by the carrier signals by means of the digital filter. Such limiting of the bands and multiplication by the carrier signals are carried out by the digital filter in a time-divisionally multiplexed manner. The digital filter includes a circuit, for accumulating symbol mapping data for each of the I phase and the Q phase corresponding to a plurality of symbol sections, a plurality of ROMs corresponding to the plurality of symbol sections for storing a multiplication result of symbol data corresponding to a predetermined filter waveform and the carrier signal, and an adder for adding data output from these ROMs. The adder outputs a digital modulated signal which is, in turn, converted into an analog modulated signal by a D/A converter.

Digital DQPSK modulator

Apparatus for demodulating an incoming digitally phase modulated analog signal to reproduce symbol data carried by the signal. Specifically, the demodulator relies on first counting, on a free-running and modulo basis, pulses of a fixed-frequency reference clock signal to form a counted value. The incoming signal is converted to a one-bit phase modulated digital signal. At the occurrence of a pre-defined point in the one-bit phase modulated signal, typically a rising edge occurring at the symbol rate, the counted value is stored as phase information. Within each symbol period, a difference between current and immediately prior counted values, i.e. the latter being a current value but delayed by one symbol period, is determined. This difference, i.e. phase change data, is subsequently sampled and decoded to yield reproduced symbol data, as well as, used, through a phase locked loop, to generate a data clock and the symbol clock.

Relatively simple QPSK demodulator, that uses substantially all digital

A digital modulator includes a signal source for a digital baseband signal and a signal source for carrier phase information. The digital baseband signal is converted into amplitude information of an I phase, a Q phase, an I' phase and a Q' phase by a mapping circuit. The carrier phase information is converted into four phase information with phases shifted by shift registers to be out of phase by .pi./4 from each other. The digital modulator includes four ROM, each ROM outputting a multiplication result of the corresponding amplitude information and carrier signal based on the corresponding one of the four amplitude information as a higher order address and the corresponding one of the four phase information as a lower order address. These outputs are added to each other in a digital manner and then converted into an analog signal which is supplied as a modulated signal.

Digital modulator and baseband signal generator for digital modulator

In a cellular-type communication system, a receiving apparatus of a mobile station which has received a forward control channel message recovers word synchronization of the received data. More particularly, the receiving apparatus converts serial FOCC data into a 8-bit parallel data signal while generating 8-bit parallel synchronization data indicative of a word synchronizing position in the parallel data above, and thus applies these two parallel data to a microcomputer. The microcomputer detects the synchronizing position of the synchronization data and then determines effectiveness of those data among the data signal that follow the corresponding bit position, for storing them in a memory.

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Gifu, Japan

Akio Kosaka