Fuji Electric Co., Ltd.

Fuji Electric Holdings Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Fuji Electronic Co., Ltd.

Akio Kitamura

Naoto Fujishima

Gen Tada

Masaru Saito

Masaharu Yamaji

Yoshiaki Toyoda

Kazuo Matsuzaki

Takato Sugawara

Taichi Karino

Masaru Saitou

Hiromichi Gohara

Ryoichi Kato

Mutsuo Nishikawa

Katsumichi Ueyanagi

Takafumi Yamada

Yoshitaka Nishimura

Mutsumi Kitamura

Katsuyuki Uematsu

Souichi Yoshida

Nobuhide Arai

Kohei Yamauchi

Tatsuhiko Asai

Yukio Yano

Shinichiro Adachi

Yoshihiko Nagayasu

Hajime Masubuchi

Provided is a semiconductor module comprising: a semiconductor chip; a cooling portion having a refrigerant passing portion through which a refrigerant passes; and a laminated substrate having: a first metal interconnection layer; a second metal interconnection layer; and an insulation provided between the first metal interconnection layer and the second metal interconnection layer, wherein the cooling portion has: a top plate; a bottom plate; and a plurality of protruding parts which are provided on a surface of the bottom plate, and are separated from each other in a flow direction of the refrigerant, and are respectively provided continuously in a direction orthogonal to the flow direction, wherein the plurality of protruding parts are provided at a position overlapping with one end of the second metal interconnection layer and at a position overlapping with the semiconductor chip in the flow direction.

Semiconductor module

A semiconductor device including a semiconductor element, an upper-surface electrode provided on an upper surface of the semiconductor element, a plated layer provided on an upper surface of the upper-surface electrode, one or more gate runners penetrating the plated layer and provided to extend in a predetermined direction on the upper surface of the semiconductor element, and a metal connecting plate that is arranged above the plated layer and is electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion that is connected to a first end of the joint portion and extends in a direction away from the upper surface of the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, the rising portion and the gate runner do not overlap with each other.

Semiconductor device

An integrated circuit in which a voltage divider circuit is integrated comprises a first resistor, second resistor, control portion, switch, and switching portion. The first resistor and second resistor form a resistive voltage divider element for dividing a voltage obtained by rectifying an alternating-current voltage, or a direct-current voltage, supplied to a control portion. The switch is provided in series with the resistive voltage divider element, and passes or cuts off current passing through the resistive voltage divider element. The switching portion switches the switch so as to pass current during driving of the control portion, and cut off current during standby of the control portion.

Integrated circuit and semiconductor device

A vertical super junction MOSFET and a lateral MOSFET are integrated on the same semiconductor substrate. The lateral MOSFET is electrically isolated from the vertical super junction MOSFET by an n-buried isolating layer and an n-diffused isolating layer. The lateral MOSFET is formed of a p-well region formed in an nsemiconductor layer bounded by the n-buried isolating layer and n-diffused isolating layer, an n-source region and n-drain region formed in the p-well region, and a gate electrode that covers a portion of the p-well region sandwiched by the n-source region and n-drain region. As the n-buried isolating layer is formed at the same time as an n-layer () of the vertical super junction MOSFET, it is possible to reduce cost. Also, it is possible to suppress parasitic action between the elements with the n-buried isolating layer.

Semiconductor device and manufacturing method thereof

An integrated circuit () in which a voltage divider circuit is integrated comprises a first resistor (), second resistor (), control portion (), switch (), and switching portion (). The first resistor () and second resistor () form a resistive voltage divider element for dividing a voltage obtained by rectifying an alternating-current voltage, or a direct-current voltage, supplied to a control portion (). The switch () is provided in series with the resistive voltage divider element, and passes or cuts off current passing through the resistive voltage divider element. The switching portion () switches the switch () so as to pass current during driving of the control portion (), and cut off current during standby of the control portion ().

A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFETand an enhancement type MOSFET, and has a floating structure that isolates depletion-type MOSFETand enhancement type MOSFETfrom a ground terminal. The depletion-type MOSFETand enhancement type MOSFETare connected in series to each other, wherein the depletion-type MOSFETis connected to high-potential-side terminal and the enhancement type MOSFETis connected to low-potential-side terminal. The semiconductor device having the configuration described above is disposed in a voltage detecting circuit section in a control IC for a battery including multiple cells.

The invention provides a semiconductor device exhibiting a stable and high breakdown voltage, which is manufactured at a low manufacturing cost. The semiconductor device of the invention includes an n-type silicon substrate; a p-type base region in the surface portion of substrate; an n-type drain region in the surface portion of n-type substrate; a p-type offset region in the surface portion of n-type substrate; an n-type source region in the surface portion of p-type base region; a p-type contact region in the surface portion of p-type base region; a gate electrode above the extended portion of p-type base region extending between n-type source region and n-type substrate (or p-type offset region), with a gate insulation film interposed therebetween; an insulation film on gate electrode and p-type offset region; a source electrode on n-type source region; and a drain electrode on n-type drain region. The p-type offset region is formed of a first p-type sub-region, a second p-type sub-region, and a third p-type sub-region.

Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same

A method of manufacturing a lateral trench-type MOSFET exhibiting a high breakdown voltage and including an offset drain region around a trench. Specifically, impurity ions are irradiated obliquely to the side wall of a trench to implant the impurity ions only into to the portion of a semiconductor substrate along the side wall of trench, impurity ions are irradiated in parallel to the side wall of trench to implant the impurity ions only into to the portion of semiconductor substrate beneath the bottom wall of trench; the substrate is heated to drive the implanted impurity ions to form an offset drain region around trench and to thermally oxidize semiconductor substrate to fill the trench 2 with an oxide. Alternatively, the semiconductor substrate is oxidized to narrow trench with oxide films leaving a narrow trench and the narrow trench left is filled with an oxide. Still alternatively, a plurality of trenches is formed, the trenches are filled with an oxide and the extended portion of semiconductor substrate extended between the adjacent trenches is converted to an oxide film by thermal oxidation.

Method of manufacturing semiconductor device

An over-voltage protection circuit for protecting an integrated circuit includes an external power supply terminal to which a power supply voltage is supplied, a grounding terminal to which a ground voltage is supplied, and an internal power supply terminal for supplying the power supply voltage to the integrated circuit. A voltage dividing unit is connected between the external power supply terminal and the grounding terminal for dividing a voltage supplied from the external power supply terminal, and has a Zener diode and a first resistor connected in series. A signal generating unit is connected between the external power supply terminal and the grounding terminal for outputting the power supply voltage or the ground voltage, and a switching unit is connected between the internal power supply terminal and the signal generating unit for performing a switching operation.

Over-voltage protection circuit

A plurality of trenches, about 1 &#x3bc;m long in the Z-direction that crosses the X-direction (source-drain direction), are formed in a semiconductor substrate, arranged in the Z-direction. Ion implantation is performed obliquely with respect to side faces of each trench that cross the X-direction. Then, ion implantation is performed perpendicularly to the bottom face of each trench. Then, oxidation and drive-in are performed, whereby semiconductor portions between adjacent trenches are oxidized and each trench is thereby filled with an oxide to establish a wide trench region as would be obtained by connecting the trenches. At the same time, the impurity ions implanted around the trenches are diffused also in the Z-direction, whereby a uniform offset drain region is formed around the trench so that an optimum concentration and diffusion of the impurity ions is obtained, and an oxide or the like is buried in a wide trench region.

Manufacturing method of a semiconductor device

A submicron CMOS transistor is mounted on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components. When a punch-through stopper area is formed on a main surface side of a semiconductor substrate, an area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed is masked, and for example, an ion injection is then carried out. Thus, a punch-through stopper area is formed in the area in which a submicron CMOS transistor is formed, while preventing the formation of a punch-through stopper area in the area in which an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor is formed.

Growing community of inventors

Nagano, Japan

Akio Kitamura