Sony Corporation

Akio Kayanuma

Minoru Nakamura

Hiroyuki Miwa

Kenji Katori

Go Sudo

Hayato Hommura

Hiroshi Matsuki

Katsuaki Asano

Koji Kobayashi

Takayuki Gomi

Takashi Shimada

Hiroaki Anmo

Hiroki Hozumi

Norikazu Ouchi

Norikazu Chuchi

Shinishi Saiki

A method of preparing composite materials by (a) containing particulates to which an adhering material is to be made to adhere, in a rotary body having a bottom surface and a side wall; (b) rotating the rotary body so as to apply centrifugal forces to the particulates in the rotary body; and (c) varying the inclination of the rotary body to an arbitrary inclination angle in the range from an angle at which the bottom surface of the rotary body forms a horizontal surface perpendicular to the direction of gravity to an angle at which the bottom surface forms a vertical surface parallel to the direction of gravity, and supporting the rotary body at the arbitrary inclination angle.

Apparatus and method for preparing composite particulates

Disclosed herein is an apparatus for preparing composite particulates, including a rotary body having a bottom surface and a side wall and operative to contain particulates to which an adhering material is to be made to adhere; a centrifugal machine for rotating the rotary body so as to apply centrifugal forces to the particulates in the rotary body; and an inclination varying device operative to vary the inclination of the rotary body to an arbitrary inclination angle in the range from an angle at which the bottom surface of the rotary body forms a horizontal surface perpendicular to the direction of gravity to an angle at which the bottom surface forms a vertical surface parallel to the direction of gravity, and operative to support the rotary body at the arbitrary inclination angle.

Apparatus and method for preparing composite particulates using vapor deposition

A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter region are formed within the semiconductor substrate. A method of fabricating a semiconductor device comprises a step of forming a collector region of a second conduction type and an emitter region of a second conduction type in a lateral arrangement in a semiconductor substrate serving as a base region of a first conduction type by using a first mask provided with a pair of openings, and a step of forming heavily doped regions of the second conduction type so as to be connected respectively to the collector region and the emitter region by using a second mask provided with a pair of openings separated from each other by a distance greater than the distance between the openings of the first mask.

Semiconductor device having enhanced impurity concentration profile

A bipolar integrated circuit having a polysilicon contact (26) to a heavily doped graft base region 24g which is spaced from oxide isolation walls 22 by a distance sufficiently small that in operation, the surface portion 37 of the collector region 23 is fully depleted from the graft base region 24g to the oxide isolation 22, so that base-collector capacitance is reduced due to the graft base being smaller than the oxide isolated island and by the absence of capacitance between the sides of the graft base region and the collector, while capacitance between the polysilicon contact 26 and the collector is also decreased by the depleted surface portion 37 of the collector.

Bipolar transistor with reduced parasitic capacitance

In a semiconductor device having trench-shaped element isolating regions formed in a semiconductor body and also a conductive layer extending on each element isolating region and connected to an impurity diffusion region of the semiconductor body, there is formed an insulator layer region between an extension of the conductive layer and the element isolating region, and the insulator layer region is buried in the surface portion of the semiconductor body. In such construction, the insulation space between the conductive layer and the semiconductor body can be increased while the distance between the element isolating region and the impurity diffusion region can be shortened to consequently diminish the parasitic capacitance between the conductive layer and the semiconductor body, hence attaining a faster operation in the semiconductor device. When the present invention is applied to a bipolar transistor integrated circuit, a superfast operation is ensured due to the reduction of the base-to-collector capacitance.

Semiconductor device made with a trenching process

Method for manufacturing a semiconductor device utilizing self-aligned

Method for manufacturing a semiconductor device

A semiconductor device is disclosed which has a first semiconductor layer of one conductivity type and low impurity concentration, a second semiconductor region of the opposite conductivity type forming a PN junction with the first semiconductor layer, a third semiconductor region of the first mentioned conductivity type formed in the first semiconductor layer which surrounds the PN junction and forms an LH junction with the first semiconductor layer, a passivating layer covering at least the PN and LH junctions, and a conductive layer extending on the passivating layer covering at least the inner periphery of the third region and connected to the first semiconductor layer through an electric barrier layer.

Semiconductor device having at least one PN junction and channel stopper

Growing community of inventors

Kanagawa, Japan

Akio Kayanuma