Sharp Kabushiki Kaisha Corporation

Akio Kawamura

Katsuji Iguchi

Kenichi Azuma

Shinichi Sato

Shigeki Hayashida

Yoshiji Takamura

Masahiko Urai

Akito Konishi

Tomohiko Tateyama

Takahiro Tsuchida

A semiconductor device comprises a first insulating film which is formed on a semiconductor substrate and has a groove whose bottom does not reach said semiconductor substrate, and a capacitive element which is composed of a lower electrode of a first metal layer which is embedded in said groove, a capacitive insulating film of a second insulating film formed on said lower electrode, and an upper electrode of a second metal layer formed in a region where both said lower electrode and said capacitive insulating film are formed.

Semiconductor device and production process thereof

A semiconductor device comprises:a semiconductor substrate; a plurality of active regions for forming semiconductor elements, the active regions being formed on the semiconductor substrate; a device isolation region for separating the plural active regions from each other, the device isolation region including a trench region filled with an insulating film and a pseudo active region formed adjacent to the trench region; a wiring layer formed above the semiconductor substrate; and a pseudo conductive film formed on the device isolation region, wherein, if the pseudo conductive film is partially or entirely located under the wiring layer, the pseudo conductive film is formed only on the trench region.

Semiconductor device and a process for manufacturing the same

A method of manufacturing a semiconductor device comprises; forming a device isolation region in a semiconductor substrate; forming at least a first conductivity type impurity region in the semiconductor substrate; and forming on the semiconductor substrate a transistor including a gate insulating film, a gate electrode, source/drain regions and a channel located directly under the gate electrode, wherein the first conductivity type impurity region is formed by the steps of: an ion implantation 1 having a concentration peak at a location deeper than the bottom of the device isolation region; an ion implantation 2 having a concentration peak at a location around the bottom of the device isolation region; an ion implantation 3 having a concentration peak around the junction regions where the source/drain regions are to be formed; and an ion implantation 4 having a concentration peak on the surface or directly under the surface of the region where the channel is to be formed.

Method for manufacturing a semiconductor device

An MOS transistor comprises a semiconductor substrate having a field region; a gate electrode formed on the semiconductor substrate through the intermediatry of a gate insulating film; and source/drain regions formed in the semiconductor substrate; wherein the field region including at least a lower insulating film and an upper insulating film made of a material permitting the upper insulating film to be selectively etched with respect to the lower insulating film; the gate electrode being configured such that the gate length of a top surface thereof is greater than the gate length of a bottom surface thereof facing a channel region positioned between the source/drain regions; the gate electrode having a sidewall spacer formed of a sidewall insulating layer made of the lower insulating film and a material permitting the sidewall insulating layer to be selectively etched with respect to the upper insulating film, the sidewall spacer contacting a side wall of the gate electrode for covering an outer periphery of the channel region; and the channel region being substantially leveled with the source/drain regions.

MOS transistor and fabrication process therefor

A semiconductor device which comprises plural memory cells, said memory cell comprising: a flip-flop circuit including a pair of drive transistors each having a gate, a gate oxide film and source/drain regions, and a pair of load TFTs connected to said pair of drive transistors, each of said load TFTs having a gate electrode, a gate oxide film and an active layer including source/drain regions all of which are deposited sequentially in that order; and a pair of access transistors connected to said flip-flop circuit; wherein either one of the source/drain regions of said each TFT is connected to at least either one drive transistor at either one of the source/drain regions thereof or the other drive transistor at the gate thereof via a semiconductor pad, and the other of the source/drain regions of the TFT is connected to a wiring layer via a semiconductor pad; and at least surface layer of said semiconductor pad has the same conductivity type as that of the source/drain regions of the TFT.

Semiconductor memory device including thin-film load transistors

Element isolation regions are first formed on a silicon substrate. Active regions other than the isolation regions are formed with an oxide film. Then, a first oxidization prevention layer, a semiconductor layer and a second oxidization prevention layer are formed on the substrate in that order. A resist pattern having a hole in a P-channel MOS transistor formation region is formed. The second oxidization prevention layer in the P-channel MOS transistor formation region is removed and an impurity is ion-implanted using the resist pattern as a mask. After removing the resist pattern, the substrate is thermally treated in the presence of an oxidizer substance to transform an exposed portion of the semiconductor layer into an oxidized semiconductor layer and at the same time to diffuse the implanted impurity in the substrate to thereby form an N-well. After removing the remaining second oxidization prevention layer and the semiconductor layer located under the remaining second oxidization prevention layer, an impurity is ion-implanted into the substrate using the oxidized semiconductor layer as a mask, to thereby form a P-well in a N-channel MOS transistor formation region of the substrate. Then the P-channel and N-channel MOS transistors are formed in respective regions.

Semiconductor device producing method requiring only two masks for

A method for producing a semiconductor device in which an electrode and an impurity-diffused layer formed on a semiconductor substrate are electrically connected to each other, includes the following steps: forming a first insulating film on the semiconductor substrate; forming a first mask layer on the first insulating film, and forming a second mask layer on the first mask layer, the first mask layer comprising a first opening for exposing a part of the surface of the semiconductor substrate, the second mask layer comprising a second opening, at least the exposed part of the surface of the semiconductor substrate being exposed by the second opening; removing at least a part of the first insulating film exposed through the first opening; implanting a first impurity into the semiconductor substrate using the second mask layer as a mask and employing an acceleration energy at which the first impurity can pass through the first mask layer; removing the second mask layer, and forming the electrode doped with a second impurity so as to entirely cover the first opening; implanting a third impurity into the semiconductor substrate using the electrode as a mask; and activating the first impurity and the third impurity by annealing the semiconductor substrate, and diffusing the second impurity from the electrode to the semiconductor substrate by annealing the semiconductor substrate by annealing the semiconductor substrate, thereby forming the impurity-diffused layer.

Method for electrically connecting an electrode and impurity-diffused

A process for manufacturing a semiconductor device which comprises the following steps of (i) forming a first insulating film on the whole surface of a semiconductor substrate having thereon a thin conductive layer with an intervening gate insulating film, (ii) removing the first insulating film at a channel region to cause the thin conductive layer to be exposed, thereby forming an opening portion, (iii) implanting ions in the opening portion to form a channel region in the substrate, (iv) forming a gate electrode of a conductive material in the opening portion, (v) removing only the first insulating film with leaving the gate electrode as it is and then implanting ions by using the gate as a mask to form a low carrier density region in the substrate, (vi) layering a second insulating film on the substrate including the gate and then carrying out an anisotropic etching to build a sidewall of the gate electrode, and (vii) implanting ions by use of the gate electrode and its sidewall as a mask to form a high carrier density region on the substrate, whereby completing an insulating gate type of field effect transistor having a low carrier density region for mitigating field effect, the low carrier density region adjoining to source and drain regions of high carrier density.

Process for manufacturing semiconductor device

An isolator for isolating semiconductor devices, components of an integrated circuit, on a semiconductor substrate, wherein the isolator is delimited by walls of a trench formed on a top surface of the semiconductor substrate, and the trench is filled with a silicon oxide layer deposited by a chemical vapor deposition method. A small ditch created in the middle of a top surface of the silicon oxide layer in the trench is filled with silicon, and at least a top surface of the silicon is thermally oxidized to form another silicon oxide layer.

Isolator for electrically isolating semiconductor devices in an

A method for forming a semiconductor device isolation region including steps of forming a first silicon oxide film on a silicon substrate, depositing a first silicon nitride film over the first silicon oxide film, and removing the first silicon oxide film and first silicon nitride film in a device isolation region by using a resist pattern, which is formed by a one-time photolithographic step, as a mask so as to expose the surface of the silicon substrate, removing the resist pattern, and oxidizing the exposed surface of the silicon substrate so as to form a second silicon oxide film having a smaller thickness than the first silicon oxide film and to deposit a second silicon nitride film, removing the second silicon nitride film by anisotropic etching until the second silicon oxide film is exposed in the device isolation region so as to make the second silicon nitride film remain as the side wall portion of the silicon nitride film in only the opening side wall portion of the first silicon nitride film, etching the second silicon oxide film in the opening of the first silicon nitride film on a self-aligning basis by using as etching masks the first silicon nitride film and the side wall portion of the second silicon nitride film remaining on the opening side wall portion of the first silicon nitride film, and selectively carrying out oxidation so as to form a thick silicon oxide film in the device isolation region.

Method for forming a semiconductor device isolation region

A method for forming semiconductor device isolation regions including steps of forming a first insulating film on a semiconductor substrate, removing the first insulating film in a portion to become a device isolation region with use of a resist pattern formed in a one-time lithography step as a mask so as to form an opening which reaches the semiconductor substrate, removing the resist pattern to deposit a second insulating film on the first insulating film and the inside of the opening and then etching the entire surface in order to make the second insulating film remain on only the periphery of the bottom of the opening and to expose the surface of the semiconductor substrate in a central portion of the bottom of the opening, forming an oxide film on the surface of the semiconductor substrate exposed in the central portion of the bottom of the opening with use of the first insulating film and the second insulating film on the periphery of the bottom of the opening as a mask by a selective oxidation method, removing the second insulating film on the periphery of the bottom of the opening and then etching the surface of the semiconductor substrate exposed on the periphery of the bottom of the opening with use of the oxide film formed in the central portion of the bottom of the opening by the selective oxidation method and the first insulating film which remains in portions other than the device isolation region as a mask so as to form a trench, and burying the trench with a third insulating film.

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Nara, Japan

Akio Kawamura