Fujitsu Corporation

Fujitsu Microelectronics Limited

Akio Itoh

Yukinobu Hikosaka

Takashi Ando

Naoya Sashida

Junichi Watanabe

Wataru Yokozeki

Masaki Aoki

Ko Nakamura

Kazuaki Takai

Takashi Eshita

Takeyasu Saito

Kenkichi Suezawa

Jiro Miura

Mitsuteru Mushiga

To provide a semiconductor device capable of improving accuracy in finishing a hole in which a conductive plug right under a capacitor, and a manufacturing method of such a semiconductor device comprising the following steps: a step of forming first and second conductive plugsin first and second holesin a first insulating film; a step of forming a first openingin an oxidation preventing insulating film; a step of forming an auxiliary conductive plugin the first opening; a step of forming a capacitor Q on the auxiliary conductive plug; a step of forming third and fourth holesin a second insulating filmcovering the capacitor Q; a step of forming the second openingin the oxidation preventing insulating filmunder the fourth hole; a step of forming a third conductive plugin the third hole; and a step of forming a fourth conductive plugin the third hole

Semiconductor device and manufacturing method of the same

There are contained first and second conductive plugs formed in first insulating layer, an island-like oxygen-barrier metal layer for covering the first conductive plug, an oxidation-preventing insulating layer formed on the first insulating layer to cover side surfaces of the oxygen-barrier metal layer, a capacitor having a lower electrode formed on the oxygen-barrier metal layer and the oxidation-preventing insulating layer, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, a second insulating layer for covering the capacitor and the oxidation-preventing insulating layer, a third hole formed in respective layers from the second insulating layer to the oxidation-preventing insulating layer on the second conductive plug, and a third conductive plug formed in the third hole and connected to the second conductive plug.

Semiconductor device and method of manufacturing the same

There is provided a semiconductor device which is manufactured via steps of forming a capacitor which is obtained by forming in sequence an upper electrode, a dielectric film formed of ferroelectric material or high-dielectric material, and a lower electrode on a semiconductor substrate, then forming an interlayer insulating film on the capacitor, then planarizing a surface of the interlayer insulating film by the CMP polishing, then removing a moisture attached to a surface of the interlayer insulating film or a moisture contained in the interlayer insulating film by applying the plasma annealing using an NO gas, and then forming a redeposited interlayer film on the interlayer insulating film.

A nonvolatile semiconductor memory device includes a substrate, a plurality of transistors formed on the substrate to constitute a latch, a plate line, and a pair of capacitors each including a lower electrode, a ferroelectric film, and an upper electrode, the pair of capacitors being provided in a layer situated above the substrate and below a metal wiring layer in which the plate line is formed.

Nonvolatile semiconductor memory device with stable ferroelectric capacitor

Semiconductor memory device having planarized upper surface and a SiON moisture barrier

A semiconductor device having conductive plug for connecting capacitor and conductive pattern, comprises first and second impurity diffusion regions formed in a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a first hole formed in the first insulating film on the first impurity diffusion region, a first conductive plug formed in the first hole and made of a metal film, a second hole formed in the first insulating film on the second impurity diffusion region, a second conductive plug formed in the second hole and made of conductive material that is hard to be oxidized rather than the metal film, and a capacitor that consists of a lower electrode connected to an upper surface of the second conductive plug, a dielectric film, and an upper electrode.

The source region and gate electrode of a field effect transistor including a drain region and a gate electrode in addition to the source region are connected by a first ferroelectric capacitor. The drain region and gate electrode are connected by a second ferroelectric capacitor. A ferroelectric memory device suitable for high integration is provided.

Growing community of inventors

Kawasaki, Japan

Akio Itoh