Mitsubishi Electric Corporation

Renesas Electronics Corporation

Akio Idehara

Hirotaka Motai

Yurika Terada

Hitoshi Yamamoto

Tomohisa Yamaguchi

Takehisa Mizuguchi

Hiroki Konaka

Shinichi Ochiai

Yasuhiro Tawara

Ryohei Kuba

Bampei Kaji

Toshiyuki Otani

A slave node () is slave equipment that operates in accordance with a control frame transmitted from a master node (). The slave node calculates a control frame statistic that is a statistic of one or more control frames transmitted from the master equipment and estimates a master environment value based on the calculated control frame statistic. The slave node measures a slave environment value. The slave node estimates a frequency deviation of a master clock based on the estimated master environment value and estimates a frequency deviation of a slave clock based on the measured slave environment value. The slave node modifies a clock value of the slave clock based on a difference between the frequency deviation of the master clock and the frequency deviation of the slave clock.

Slave equipment, computer readable medium, and embedded system

In an information processing apparatus (), obtaining units such as a first obtaining unit () and a second obtaining unit () obtain general-purpose OS information in a test operation phase in which a real-time application and a plurality of general-purpose applications are executed. The general-purpose OS information is information on use of hardware by each of the plurality of general-purpose applications executed in the test operation phase. A management unit () verifies whether or not a condition to place a restriction on the use of the hardware is satisfied for each general-purpose application based on the general-purpose OS information obtained by the obtaining unit. The management unit (), when the condition is verified as being satisfied, places a restriction on the use of the hardware for an applicable general-purpose application in an actual operation phase in which the real-time application and the plurality of general-purpose applications are executed.

Information processing apparatus, tuning method, and computer readable medium

A built-in apparatus includes a response time buffer () that stores a response time, a calculation result buffer () that stores a calculated frame, and a transmission part (). The transmission part () obtains second data and start processing for calculating a frame check sequence from the second data, upon receiving a transmission command (), judges whether frame transmission processing for generating and transmitting the second data and the frame check sequence calculated from the second data as a response frame () will be completed within the response time, and transmits the calculated frame stored in the calculation result buffer () as the response frame () when judging that the frame transmission processing will not be completed within the response time.

Built-in apparatus, communication method, and computer readable medium

Timers #through #are each supplied with a period for prohibiting a change in a power supply voltage. An OS #A or an OS #B determines necessity to change an operating frequency for a CPU core corresponding to any of the timers #through #when the timer exceeds the prohibition period. It is determined whether it is necessary to change a power supply voltage supplied to CPU cores #through #when the OS #A or the OS #B determines necessity to change an operating frequency. When it is determined that a power supply voltage needs to be changed, a power supply voltage change portionchanges the power supply voltage supplied to the CPU cores #through #. Therefore, it is possible to improve the processing efficiency without needing to acquire inter-OS lock.

Multiprocessor for providing timers associated with each of processor cores to determine the necessity to change operating frequency and voltage for per core upon the expiration of corresponding timer

Growing community of inventors

Tokyo, Japan

Akio Idehara