Growing community of inventors

Hachiouji, Japan

Akio Hayakawa

Average Co-Inventor Count = 9.00

ph-index = 6

The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.

Forward Citations = 111

Akio HayakawaKiyoshi Matsubara (7 patents)Akio HayakawaAtsushi Hasegawa (7 patents)Akio HayakawaYasushi Akao (7 patents)Akio HayakawaKouki Noguchi (7 patents)Akio HayakawaKeiichi Kurakazu (7 patents)Akio HayakawaShumpei Kawasaki (7 patents)Akio HayakawaHiroshi Ohsuga (7 patents)Akio HayakawaYoshitaka Ito (7 patents)Akio HayakawaAkio Hayakawa (7 patents)Kiyoshi MatsubaraKiyoshi Matsubara (62 patents)Atsushi HasegawaAtsushi Hasegawa (61 patents)Yasushi AkaoYasushi Akao (52 patents)Kouki NoguchiKouki Noguchi (45 patents)Keiichi KurakazuKeiichi Kurakazu (34 patents)Shumpei KawasakiShumpei Kawasaki (27 patents)Hiroshi OhsugaHiroshi Ohsuga (13 patents)Yoshitaka ItoYoshitaka Ito (7 patents)
..
Inventor’s number of patents
..
Strength of working relationships

Company Filing History:

1. Hitachi, Ltd. (5 from 42,485 patents)

2. Other (2 from 832,680 patents)

3. Hitachi Ulsi Engineering Corp. (1 from 87 patents)


7 patents:

1. 6748507 - Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory

2. 6735683 - Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements

3. 6591294 - Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals

4. 6279063 - Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller

5. 6223265 - Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal

6. 6212620 - Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals

7. 5930523 - Microcomputer having multiple bus structure coupling CPU to other

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12/6/2025
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