Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Hitachi Ulsi Systems Co., Ltd.

Akita Electronics Systems Co., Ltd.

Akio Hasebe

Asao Nishimura

Kunihiko Nishi

Kunihiro Tsubosaki

Ichiro Anjoh

Aizo Kaneda

Shozo Nakamura

Hiroshi Kikuchi

Takashi Yokoyama

Gen Murakami

Makoto Kitano

Akihiro Yaguchi

Takashi Yamazaki

Hiroshi Hozoji

Kazuyoshi Oshima

Masahiro Ichitani

Junichi Saeki

Isamu Yoshida

Sueo Kawai

Hiroyoshi Kokaku

Noriyuki Kinjo

Masatsugu Ogata

Masanori Segawa

Syuuji Eguchi

Yasunori Narizuka

Yasuhiro Motoyama

Hideki Tanaka

Ichiro Anjo

Chuichi Miyazaki

Tetsuro Matsumoto

Ryosuke Kimoto

Yukiharu Akiyama

Tomoaki Kudaishi

Masanori Shibamoto

Tetsurou Matsumoto

Yoshinori Deguchi

Masayoshi Okamoto

Susumu Kasukabe

Shingo Yorisaki

Hideyuki Matsumoto

Bunji Yasumura

Naohiro Makihira

Mitsuyuki Kubo

Fumikazu Takei

Teruo Shoji

Seigo Nakamura

Akira Yabushita

Yuji Wada

Takehiko Hasebe

Akira Shimase

Kenji Kawakami

Terutaka Mori

Naoki Okamoto

Masnori Shibamoto

Masakazu Sueyoshi

Akira Nagai

Hiroyuki Ohta

Masahiko Ogino

Kenichi Yamamoto

Naotaka Tanaka

Shuji Eguchi

Ryuji Kohno

Masao Mitani

Akira Mitsui

Shigeharu Tsunoda

Hideo Arima

Naoto Ban

Hiroshi Koyama

Ryuji Shibata

Masaaki Namba

Takehiro Ohnishi

Noriou Shimada

Yuji Takeda

Akira Seito

Isamu Masumoto

Motoji Murakami

Yoshiaki Hasegawa

Toshiyuki Majima

To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Method for manufacturing semiconductor device

Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

Method of manufacturing semiconductor device

A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.

Manufacturing method of semiconductor integrated circuit device

A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

Method of manufacturing a semiconductor integrated circuit device and a method of manufacturing a thin film probe sheet for using the same

To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

Fabrication method of semiconductor integrated circuit device

As the thickness of the card holder for preventing warping of a multilayered wiring substrateis increased, there occurs a problem that a thin film sheetis buried in a card holder and secure contact between probesand test pads cannot be realized. For its prevention, the thin film sheetand a bonding ringare bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ringdefining the height up to the probe surface of the thin film sheetis increased, thereby increasing the height up to the probe surface of the thin film sheet

A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.

Method of manufacturing a semiconductor integrated circuit device

By using a membrane probe formed by using a manufacturing technique for semiconductor integrated circuit devices, the yield of probing collectively performed on a plurality of chips is to be enhanced. A probe card is formed by using a plurality of pushers, each pusher being formed of a POGO pin insulator, POGO pins, an FPC connector, a membrane probe HMS, an impact easing sheet, an impact easing plate, a chip condenser YRS and so on, wherein one or two POGO pins press a plurality of metal films arranged like islands. One or more cuts are made into what matches the chip to be tested in the area of the membrane probe in a direction substantially parallel to the extending direction of wiring electrically connected to probes formed in the membrane probe.

Electrical testing is to be performed on a semiconductor integrated circuit device which the test pads formed. To facilitate such testing, the method of manufacture of the semiconductor integrated circuit device employs a probe card which has two or more contact terminals which can contact two or more electrodes. This probe card includes, in opposition to a wiring substrate of the semiconductor integrated circuit device in which a first wiring is formed, a first sheet having two or more contact terminals to contact the two or more electrodes; a second wiring electrically connected to the two or more contact terminals and the first wiring; and first dummy wirings which are near the region of formation of the two or more contact terminals, are arranged to a non-forming region of the second wiring, and do not participate in signal transfer.

Manufacturing method of semiconductor integrated circuit device and probe card

Growing community of inventors

Kodaira, Japan

Akio Hasebe