Kabushikikaisha Kenwood

Nippon Hoso' Kyokai

Other

Mitsubishi Electric Corporation

Akebono Brake Industry Co., Ltd.

Akinori Hashimoto

Hisakazu Katoh

Tomohiro Saito

Kenichi Shiraishi

Akihiro Horii

Fumiaki Minematsu

Shoji Matsuda

Shoji Tanaka

Soichi Shinjo

Hajime Matsumura

Shigeyuki Itoh

Yoichi Suzuki

Masanori Kato

Hiroshi Idei

Junji Kumada

Kazuhiko Shibuya

Yuichi Iwadate

Kazuyoshi Shogen

Hisashi Sujikai

Shinsaku Kusube

Takeshi Kimura

Youichi Suzuki

Yoshiyuki Sugai

Toshihiro Nomoto

Kenichi Tsuchida

Kyoichi Saito

Tomohiro Mori

Hiroyuki Hamada

Kouichi Takano

Hiroyuki Hamazumi

Hisao Kamii

Masaru Takechi

Yoshifumi Matsusaki

Motoshi Nasu

Shoji Matuda

Kohei Ueno

An outdoor unit of an air-conditioning apparatus includes: a refrigerant circuit in which a compressor and an outdoor-side heat exchanger are connected by a refrigerant pipe; an outdoor-side fan that sends air to the outdoor-side heat exchanger; and a controller including an inverter circuit configured to drive the compressor. The controller includes: a first heat generating component; a second heat generating component that generates a smaller amount of heat than the first heat generating component; a temperature detection circuit provided in the first heat generating component to detect a temperature thereof; a temperature acquisition module that acquires the temperature detected by the temperature detection circuit; and an estimate calculation module that calculates a temperature estimate of the second heat generating component based on the temperature acquired by the temperature acquisition module, and calculates an estimate of a life of the second heat generating component based on the temperature estimate.

Outdoor unit of air-conditioning apparatus

A harmonic current compensator is connected in parallel with a harmonic generating load to a system power supply and supplies a compensation current Ia to limit a harmonic component contained in a load current IL to be input from the system power supply to the harmonic generating load. The harmonic current compensator includes: a load current detector that detects the load current IL; a compensation current detector that detects the supplied compensation current Ia; a control amount computing portion that computes a control amount of the compensation current Ia based on the harmonic component contained in the load current IL detected by the load current detector and the compensation current Ia detected by the compensation current detector; and a limiter that limits an upper limit of the compensation current Ia.

Harmonic current compensator and air-conditioning system

A transmission device and reception device for digital data that have excellent resistance to noise are provided. An encoder (-) of this disclosure, included in a transmission device () of this disclosure, applies LDPC encoding to digital data using a unique check matrix for each code rate by using a check matrix in which, taking a check matrix initial value table established in advance for each code rate at a code length of 44880 bits as initial values, 1 entries of a partial matrix corresponding to an information length appropriate for a code rate of 93/120 are allocated in the column direction over a cycle of 374 columns. A demodulator () of this disclosure, included in a reception device () of this disclosure, decodes digital data encoded by the encoder (-).

Encoder, decoder, transmission device, and reception device

To provide a digital data transmitting apparatus and a digital data receiving apparatus that can realize, even when a transmission channel characteristic changes because of aged deterioration or the like of a relay, improvement of a reception performance following the change. A transmitting apparatusgenerates a multiplexing frame formed by N slots including control information, data, outer parities, stuff bits, and inner parities and added with synchronization, pilot, and a transmission control signal and a parity and transmits data of the respective slots in a transmission system designated by the transmission control signal. In this case, pilot signals are symbols allocated to all signal points in order determined in advance for each of modulation schemes. A receiving apparatusrewrites a phase error tableto calculate a phase error and performs synchronous detection according to the pilot signals. The receiving apparatusalso rewrites a likelihood tableto perform inner code decoding. Consequently, since reception processing adapted to distortion of a transmission channel characteristic can be performed, improvement of a reception performance can be realized.

Digital data transmitting device and digital data receiving device

A method for producing a solid lubricant includes steps of preparing and coating. A phosphate aqueous solution prepared by the step of preparing is an aqueous solution containing at least one of aluminum dihydrogen phosphate and magnesium dihydrogen phosphate in an amount of 0.5 to 10% by mass. A graphite material is coated with a phosphate using the phosphate aqueous solution. The graphite material is used at a ratio of 40 to 50 parts by mass based on 100 parts by mass of the aqueous solution.

Solid lubricant and production method thereof

Digital data transmitting apparatus and digital data receiving apparatus

An iron member having a coating film on at least part of its surface is manufactured by a step of projecting zinc particles to the surface of a base material made of an iron material to form a base film, and a step of forming a coating film of resin coating material on at least a part of the base film.

Method of manufacturing iron member

A digital demodulator which will need no absolute phasing circuit is provided. A known-pattern BPSK signal generating circuit generates the same known-pattern BPSK signal as a known-pattern BPSK signal in a received digital modulated wave in synchronism with the known-pattern BPSK signal in the received digital modulated wave, a carrier-reproducing phase error detecting circuit has a phase error table where one of reference phases in a signal point position of a demodulation baseband signal is made a convergence point, a phase error voltage corresponding to a phase error between a phase determined from the signal point position of the demodulation baseband signals and a phase convergence point is sent out, by enable-controlling a carrier-reproducing loop filter according to the known-pattern BPSK signal outputted from the known-pattern BPSK signal generating circuit , the phase error voltage is smoothed, and carrier reproduction is performed while controlling the frequency of a reproduced carrier according to the smoothed output so that the phase in the signal point position coincides with the phase convergence point.

Digital demodulator

After receiving a time division multiplex signal including a plurality of digital data signals transmitted in accordance with different transmission schemes, the received time division multiplex signal is demodulated by a demodulation circuit, and it is judged by a detection circuit whether each of the demodulated digital data signals is received correctly or not. When it is detected that a digital data signal transmitted by any one of the plurality of different transmission schemes is not received correctly, the relevant digital data signal is replaced by a suitable signal such as a null packet signal which does not affect a correct reception of the remaining digital data signals transmitted by the remaining transmission schemes to form a corrected time division multiplexed signal even if a digital data signal is not received correctly.

Digital data receiver

A digital broadcasting receiver is provided which can reproduce a carrier quickly and capture a desired signal at high speed. A carrier reproduction phase error detection circuit ( ) detects a phase error voltage in accordance with a demodulation output obtained by demodulating a demodulated wave of a modulated wave during a predetermined section in a header section. A peak number calculation circuit ( ) calculates an error frequency between a desired reception frequency and a reproduction carrier frequency in accordance with the phase error voltage. A differential coefficient calculation circuit ( ) calculates the polarity of the error frequency. A step frequency control circuit ( ) converts the calculated error frequency having the calculated polarity into a step frequency width for automatic frequency control. The reproduction carrier frequency is scanned at the converted step frequency width until a frame sync is established after the frame sync is detected. It is therefore possible to reproduce the carrier quickly and capture the desired signal at high speed.

Digital broadcasting receiver

A receiver is constructed so that it detects a short-break of a digital broadcasting wave by the absence of a synchronizing code or by a transmission control signal multiplexed with the broadcasting wave and, according to the short-break detection signal, holds data and state information (program arrangement, and reference time information) obtained by an antenna and converter ( ), tuner and digital decoding portion ( ), an error correction code decoding portion ( ), a stream multiplexed signal separating portion ( ), an audio/video decoding portion ( ) and the other components and performs a process for optimally changing characteristics of closed loops for establishing synchronization.

Digital broadcast receiving system for detecting short-breaks and holding information based on same

A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit ( ), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180&deg;, which are included in a carrier reproduction phase difference detecting circuit ( ), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit ( ) so that the phase obtained from the signal point position coincides with the phase convergence point.

Carrier reproduction circuit

A hierarchical transmission digital demodulator capable of stable sync capture and stable demodulation through setting of a demodulation operation in accordance with a reception C/N value. A CNR measuring circuit receives a demodulation output from an arithmetic circuit and measures a reception C/N value. During a period until sync is captured, a carrier is reproduced in accordance with the demodulation output that a modulated wave in a header section and a modulated wave of burst symbol signal. After sync is captured, at an intermediate C/N value the carrier is reproduced in accordance with the demodulation output of the header section, burst symbol signal and QPSK signal and in accordance with output from a logical gate circuit, and at high and low C/N values the carrier is reproduced by setting high a carrier reproduction loop gain of a gain control circuit in accordance with a signal from the logical gate circuit.

Hierarchical transmission digital demodulator

A digital demodulator that eliminates the need for an absolute phase circuit is provided. In a digital demodulator for a digital broadcasting receiver that receives digital time-division multiplexed signals of different types of modulation, the demodulated baseband signal is selectively inverted by an inverter ( ) according to an inversion command signal &ldquo;0&rdquo; or &ldquo;1&rdquo; that is output from an inversion decision circuit ( ) depending on a BPSK signal of a known pattern. A phase error detector ( ) for carrier reproduction determines the phase error voltage based on the phase difference between the absolute phase and the phase of the signal point of the demodulated baseband signal output from the inverter ( ). The phase error voltage is passed through a carrier filter ( ), including a low-pass filter, to control the carrier frequency so that carrier reproduction can be carried out with the phase at the signal point being coincident with the point of phase convergence.

There is provided a synchronization acquiring circuit for stably acquiring frame synchronization without pseudo-synchronization lock when the frame synchronization is acquired in reception at the time of a low C/N. The synchronization pattern of a received frame is detected by a frame synchronization detecting circuit . The bits of the synchronization pattern of the received frame are compared with those of a frame synchronization pattern on the transmitting side by a frame synchronizing circuit to obtain the number of coincided bits. The frame synchronization is regarded as detected when the obtained number of bits of each frame is equal to or larger than the correlation detection value.

Growing community of inventors

Tokyo, Japan

Akinori Hashimoto