Seiko Epson Corporation

Other

Nagoya University

Akinari Todoroki

Katsuya Tanaka

Noboru Ninomiya

Hiroaki Takada

Yoshiyuki Ono

Shinya Honda

Akihiko Yajima

Tsunemori Asahi

Akihiko Tamura

Masakazu Isomura

Shoji Hoshina

Fumihito Baisho

Takahiro Amari

The image processing device stores a fixed horizontal resolution and a fixed vertical resolution established in advance for use in resolution conversion of an input image. The first resolution converter of the image processing device converts the input image to a fixed resolution-converted image so that at least a horizontal resolution of the fixed resolution-converted image is equal to the fixed horizontal resolution. The second resolution converter of the image processing device converts the fixed resolution-converted image output from the first resolution converter to the display resolution-converted image having the desired horizontal and vertical resolutions.

Projector, image display system, and image processing system

In at least one embodiment of the disclosure, a projector comprises an imaging unit that photographs a projection surface and acquires a first photographed image during a projection of a featured image at a first time point and acquires a second photographed image during the projection of the featured image at a second time point different from the first time point. An image processing unit generates a reference image based on the first photographed image and generates a comparative image based on the second photographed image. A movement detecting unit detects a change in a relative position of the projector with respect to the projection surface by using the reference image and the comparative image generated by the image processing unit.

Projector and method of controlling projector

A projector which displays an image by projecting a projection image onto a projection surface, includes: a fixed pixel display device for displaying the projection image in a predetermined vertical period; and an image processing device for generating the projection image in the vertical period, wherein the image processing device includes: a resolution converter which, by converting a resolution of an input image in the vertical period, generates and transmits a display image having a desired resolution; a projection distortion corrector which receives the display image, and generates the projection image by correcting the display image in the vertical period in such a way as to correct a projection distortion occurring due to a projection angle with respect to the projection surface when projecting the projection image; and a display image input/output controller which controls the reception of the display image from the resolution converter and the transmission thereof to the projection distortion corrector, wherein in the vertical period, the display image input/output controller holds the display image while receiving it from the resolution converter, during a time period from a predetermined timing prior to a start time of a process of correcting the display image by means of the projection distortion corrector to a finish time of the correction process, while it reads the display image held in advance, and transmits it to the projection distortion corrector, during a time period from the start time to the finish time of the correction process.

Projector and image processing apparatus

An image processing device includes: a first expansion unit which expands a part of first compression image data in a first predetermined area compressed as unit of compression to produce first expansion part data; a second expansion unit which expands a part of second compression image data in a second predetermined area compressed as unit of compression to produce second expansion part data; a cutting unit which cuts data in a predetermined range from the first expansion part data; a first producing unit which produces third expansion part data based on the cut data in the predetermined range and the second expansion part data; and a second producing unit which combines the second compression image data and compressed part data produced by compressing the third expansion part data in the second predetermined area as unit of compression to produce third compression image data.

Image processing device and image processing method

A projector includes a projection unit, an imaging unit, a correction control unit acquiring first correction information based on a first captured image acquired by capturing a distortion detection image projected onto a projection surface, and a distortion correction unit performing distortion correction based on the first correction information. The correction control unit, in a case where second distortion correction needs to be performed after the distortion correction unit, performs first distortion correction based on the first correction information, allows the projection unit to project the distortion detection image without transforming the distortion detection image by using the distortion correction unit allows the imaging unit to capture the projected distortion detection image so as to be acquired as a second captured image, acquires second correction information based on the second captured image, and allows the distortion correction unit to perform the second distortion correction based on the second correction information.

An image processing device and method decodes encoded image data, and converts a resolution of the decoded image data. The encoded image data is formed by encoding image data partitioned into blocks, each block including a plurality of pixels aligned in a matrix shape. The image processing device includes a decoding section that decodes and cuts out a portion of the decoded image data corresponding to a preset cut-out area and outputs the portion of the decoded image data on a block-by-block basis, a block buffer section that temporarily stores the portion of the decoded image data output, a horizontal resolution conversion section that converts the resolution of the decoded image data in the horizontal direction, a line buffer section that temporarily stores the horizontal-resolution-converted image data, and a vertical resolution conversion section that converts the resolution of the horizontal-resolution-converted image data in the vertical direction.

Image processing device

An image processing device and method decodes encoded image data, and converts a resolution of the decoded image data. The encoded image data is formed by encoding image data partitioned into blocks, each block including a plurality of pixels aligned in a matrix shape having horizontal rows and vertical columns. The image processing device includes a decoding section that decodes and outputs the decoded image data on a block-by-block basis, a block buffer section that temporarily stores, on a basis of the blocks, the decoded image data output, a horizontal resolution conversion section that converts the resolution of the decoded image data in the horizontal direction, a line buffer section that temporarily stores, on a basis of the vertical columns, the horizontal-resolution-converted image data, and a vertical resolution conversion section that converts the resolution of the horizontal-resolution-converted image data in the vertical direction.

A debug support device for debugging a multiprocessor configured by a plurality of unit processors a unit processor stop section realized by a plurality of the unit processors executing a program for each of the threads, and any one of the plurality of unit processors performing a process of stopping a unit processor executing a thread in which exception handling occurs together with unit processors executing other threads when the exception handling of software occurs by a break point of a part of the plurality of threads; and a debugging execution section for performing a debugging process of detecting information about a state of the plurality of unit processors stopped by the unit processor stop section.

Debug support device, and program for directing computer to perform debugging method

A multi-processor system with a plurality of unit processors includes: a request accepting section for accepting a first request and a second request, wherein the first request is a request to execute a program that can be executed in any of said unit processors and the second request is a request to execute a program that can be executed only in a specified unit processor among said unit processors; and a unit processor allocating section for allocating the first request and the second request accepted by said request accepting section to said unit processors according to priority of the first request and the second request.

Multi-processor system and program for causing computer to execute controlling method of multi-processor system

A multi-processor system with a plurality of unit processors includes: a semaphore setting section for setting semaphores representing preferential right to the competing of resources to be able to be identified to correspond to each of a plurality of the resources; a semaphore request determining section for determining, whether when a first unit processor among said unit processors requests to obtain a semaphore that is set to said semaphore setting section, the request is for requesting a semaphore being obtained by the second unit processor; and an exclusive controlling section for making the request by the first unit processor wait when it is determined that said request is for requesting a semaphore being obtained, and permitting to obtain the requested semaphore when it is determined that said request is for requesting a semaphore other than the semaphore being obtained by the semaphore request determining section.

Multi-processor system and program for causing computer to execute controlling method of interruption of multi-processor system

A processor includes: a plurality of processors; a process and status managing section which manages management information including information on statuses of the plurality of processors and priorities of processes being executed by the plurality of processors; a processing processor selecting section which selects one of the processors which is executing the process with a lowest priority on the basis of the management information managed by the process and status managing section; and an interrupt controlling section which transmits a requested interrupt process to the selected processor as an interrupt process request, wherein the processing processor selecting section selects the one of the processors, which is executing the process with the lowest priority, irrespective of whether each of the requested interrupt process and the processes being executed by the processors is a task process which is handled according to a predetermined schedule or an interrupt process which is handled independently of the schedule.

Processor and interrupt controlling method

A multi-processor system includes a plurality of unit processors that operate in parallel. The system includes a suspension prohibition section for, in response to a request from at least one of the unit processors, prohibiting suspension of processing only in the requesting unit processors for which prohibiting suspension has been requested. The suspension prohibition section limits the number of unit processors for which the suspension is prohibited at the same time to a certain limited number or below.

System and method for limiting the number of unit processors for which suspension of processing is prohibited

To provide a processor capable of achieving high processing efficiency by performing the exclusive control between task processing and interrupt handling properly even in a multiprocessor. An interrupt processor that includes a plurality of unit processors, in which at least of the plurality of unit processors is capable of performing interrupt handling requested from the outside is configured such that the unit processor Pof the unit processors Pto Pcomprises an purge inhibit flagfor causing the unit processor Pto enter a lock state where the purge of the task is being inhibited, a hardware semaphore unitfor inhibiting other unit processors from accessing a predetermined region in memory accessed by the unit processor Pafter the unit processor Pis brought into the lock state, and an interrupt control unitfor inhibiting the interrupt processor from performing the interrupt handling during the execution of exclusive control.

Parallel processing device and exclusive control method

A processor control device includes a processor executing an instruction, a module coupled to the processor through a bus and processing independently from the processor, the module is provided in a plural number and a polling processing unit coupled to each module, the polling processing unit stopping an operation of the processor depending on an execution status of the module processing at a time of an access request from the processor.

Processor control device for stopping processor operation

To decrease the number of arithmetical operations in a filtering process for decoding a digital signal and reduce a cost required for decoding. A filtering method for use in decoding a digital signal from a frequency domain to a time domain includes: a first step of multiplying an input data stream and a transformation matrix that is decomposed into a sparse matrix from an inverse MDCT transformation matrix for making the inverse MDCT transformation of the input data stream composed of a plurality of data blocks, and has a smaller size than the inverse MDCT transformation matrix, to acquire an output data stream composed of a plurality of data blocks; a second step of storing predetermined data contained in each data block of the output data stream; and a third step of generating the digital signal in the time domain on the basis of each data block acquired at the first step and the predetermined data stored at the second step in processing the former stage data block.

Growing community of inventors

Okaya, Japan

Akinari Todoroki