Fujitsu Corporation

Akimitsu Miyazaki

Hisaya Sakamoto

Tetsuya Kiyonaga

Nobuaki Sato

Akihiko Sugata

Takashi Kurooka

Yasunori Nagakubo

Setsuo Misaizu

Sadao Ibukuro

Tomoyuki Otsuka

Yoshinobu Miyamoto

A bias circuit for a photodetector by the present invention provides a bias voltage to the photodetector that performs electric current amplification according to the bias voltage supplied, and is characterized by comprising a power node and an auto-bias circuit that changes a time constant of the bias circuit for the photodetector according to an optical power received by the photodetector, the auto-bias circuit being connected between the power node and the photodetector, thereby reliability of operation of the photodetector is enhanced.

Bias circuit for a photodetector, and an optical receiver

In a receiving apparatus, there are included a compensation characteristic variable type waveform degradation compensating unit capable of compensating for waveform degradation of a received signal stemming from a transmission line, a received waveform measuring unit for measuring waveform data on the received signal (which will be referred to hereinafter as &ldquo;received waveform data), and a control unit for controlling a compensation characteristic of the waveform degradation compensating unit to minimize a difference between frequency data on the received signal, obtained by converting the received waveform data acquired by the received waveform measuring unit into a frequency domain, and frequency data on a reference waveform free from waveform degradation. With this configuration, certain compensation for the waveform degradation of the received signal stemming from chromatic dispersion or the like becomes feasible without using a dispersion compensation fiber.

Receiving apparatus, method of compensating for waveform degradation of received signal, apparatus and method for detecting waveform degradation, and apparatus and method for measuring waveform

An APD bias circuit includes an APD, an equalizer amplifier receiving an output signal of the APD, and first, second and third resistors connected in series to the APD to which a bias voltage is applied therethrough. A bias control circuit is connected to a first node between the first and second resistors, and receives a current from the first node so that a voltage of the first node can be maintained at a constant level. A first capacitor is connected between a ground and a second node between the second and third resistors. A second capacitor is connected between the ground and a third node between the third resistor and the APD. A first time constant defined by the second resistor and the first capacitor is greater than a second time constant defined by the third resistor and the second capacitor.

APD bias circuit

Disclosed is a clock extraction circuit for extracting a clock signal which furnishes timing for discriminating a data signal, from the data signal. The clock extraction circuit has a timing extraction unit for extracting the clock signal from the data signal, and a filter, which is provided in front of the timing extraction unit, having an upper limited frequency sufficiently lower than the bit rate of the data. The data signal is input to the timing extraction unit via the filter.

Clock extraction circuit

A clock signal detection circuit includes a diode to which a clock signal is applied as an input. If a voltage VD IN on the anode side of the diode is greater than a voltage VD OUT on the cathode side, the clock signal is fed into a transmission line and arrives at a reflecting load upon elapse of a prescribed delay time. When the voltage VD IN on the anode side of the diode becomes smaller than the voltage VD OUT on the cathode side, the clock signal is reflected by the reflecting load and returns to the cathode of the diode through the transmission line. This introduction and reflection of the clock signal is repeated at the clock signal period so that the amplitude on the output side of the diode is enlarged, thereby making it possible to obtain, from an averaging circuit, a clock detection voltage substantially equal to the amplitude value of the clock signal.

Clock signal detection circuit

An optical transmitter, a terminal-station apparatus having the optical transmitter, and an optical communication system employing the terminal-station apparatus. The optical transmitter comprises: a light-source unit for generating an optical signal; a monitor unit for monitoring a parameter depending on the wavelength of the optical signal; a judgment unit for determining as to whether or not the monitored parameter satisfies a predetermined condition; and a shut-off unit for shutting off the optical signal in case the monitored parameter does not satisfy the predetermined condition. By using the optical transmitter, it can be possible to prevent crosstalk from occurring between WDM (Wavelength Division Multiplexing) channels in the optical communication system.

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Sapporo, Japan

Akimitsu Miyazaki