Denso Corporation

Akimitsu Inoue

Kenji Yamada

Hideaki Ishihara

Shinichirou Taguchi

In a memory cell, a margin for data preservation is provided while suppressing a current consumption associated with a low-power consumption mode. A MOS transistor has the same structure as NMOS transistors included in each of memory cells. When a low-power consumption mode is designated, a voltage developed at a node is stabilized by subtracting a margin voltage for data preservation across a first resistor from a voltage applied to a first node and by subtracting a threshold voltage of the MOS transistor from the resultant voltage is applied to a second node.

Semiconductor memory device

A sub-microcomputer having a sub-CPU and a power supply control section that controls the power supply to a main microcomputer is disposed in addition to the main microcomputer having a main CPU. A sub-clock section that supplies a sub-clock signal having a lower frequency to the sub-microcomputer can change over between a continuous mode and an intermittent mode. When the main CPU gives an operation stop notification to the sub-CPU, the sub-CPU recognizes the notification, stops the power supply to the main microcomputer, and sets the sub-clock section to the intermittent mode. The sub-CPU determines that the operation state condition is satisfied in the period of the intermittent mode, the sub-CPU changes over the sub-clock section to the continuous mode to restart the power supply to the main microcomputer.

Growing community of inventors

Toyota, Japan

Akimitsu Inoue