Denso Corporation

Akimasa Niwa

Masahiro Yamamoto

Hideaki Ishihara

Tomohiro Nezuka

Yasuaki Aoki

Takuya Harada

Masahiro Kamiya

Takayuki Matsuda

Takayuki Aono

Tsuyoshi Yamamoto

Hideji Yoshida

Toshihiko Matsuoka

Yoshinori Teshima

Naoki Ito

Takahiro Iwamura

Seiji Nishimoto

Hironori Akiyama

Yuuta Nakamura

Takashi Yoshiya

Shuji Agatsuma

Kohei Shinomiya

A signal detection circuit includes: a voltage dividing circuit having at least a first pair of voltage dividing capacitors connected in series for dividing an input voltage and configured to output a divided voltage, and a detection circuit configured to detect the divided voltage. The first pair of voltage dividing capacitors are included in one semiconductor device. The semiconductor device includes: (i) a semiconductor substrate, (ii) a first conductor layer, (iii) a first dielectric layer, (iv) a second conductor layer, (v) a second dielectric layer, (vi) a third conductor layer, and (vii) a short-circuit portion configured to short-circuit the first conductor layer and the semiconductor substrate.

Signal detection circuit

A drive circuit drives a switch configuring a power converter. The drive circuit divides an inter-terminal voltage of a switch. The drive circuit includes a differential circuit having first and second input terminals to which the divided inter-terminal voltages are inputted. The differential circuit outputs an analog voltage based on a voltage difference between the input terminals. The differential circuit executes reset of the output voltage, and with the voltage difference when reset is canceled after reset is executed as a reference voltage, outputs an analog voltage in which an amount of change from the reference voltage is multiplied by an amplification factor. The drive circuit outputs a binary signal based on comparison results between a threshold and the analog voltage outputted from the differential circuit, and sets a transfer rate of a gate charge of the switch when a driving state is switched, based on the output signal thereof.

Drive circuit for switch

In a drive circuit, a differential circuit unit is configured such that resetting of an output voltage of the differential circuit unit is carried out, and the resetting of the output voltage of the differential circuit unit is cancelled. A value of the difference between first and second divided terminal voltages at a timing of cancelling the resetting is defined as a reference voltage. The differential circuit unit generates, as the output voltage, a product of a voltage change from a reference voltage and a predetermined amplification factor after cancelling of the resetting of the differential circuit unit. A signal generator generates a gate signal for the upper- and lower-arm switches in accordance with a value of the output voltage of the differential circuit unit while the upper- and lower-arm switches are in an off state.

Drive circuit for power converter

A gate drive circuit includes a driver for driving a gate of a switching element, a peak voltage detector, and a drive capacity calculator. The peak voltage detector detects a peak voltage at a main terminal of the switching element when the switching element is OFF. The drive capacity calculator calculates a voltage difference value between the detected peak voltage and an allowable voltage value at the main terminal of the switching element, where the allowable voltage is based on the specifications of the switching element. The drive capacity calculator changes a drive capacity of the driver to gradually decrease the difference between the detected peak voltage and the allowable voltage.

Gate drive circuit

A gate drive apparatus includes a driver, a peak voltage detector and a drive capability controller. The driver drives a gate of a first switching element as one of two switching elements respectively in an upper arm and a lower arm of a half-bridge circuit. The peak voltage detector detects a peak voltage at a second switching element in a situation where the first switching element is turned on. The drive capability controller calculates a value of drive capability when the driver turns on the first switching element, in a condition that the peak voltage at the second switching element does not exceed a tolerance value of a voltage at the second switching element according to a specification of the second switching element, and modifies the drive capability when the driver turns on the first switching element, based on a calculated result of the value of the drive capability.

Gate drive apparatus

A transistor drive circuit drives a bipolar-type transistor and a MOSFET that are connected in parallel to each other. A temperature detection element that detects a temperature of a the bipolar-type transistor or the MOSFET. When the temperature is equal to or less than a threshold, the transistor drive circuit turns on both of the MOSFET and the bipolar-type transistor. When the temperature exceeds the threshold, the transistor drive circuit turns on only the bipolar-type transistor.

Transistor drive circuit and motor drive control apparatus

A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.

Periodic signal processing apparatus

A microprocessor which is adapted to start a second task at a predetermined time when a first task is running if a current time becomes to be equal to the predetermined time is disclosed. The microprocessor executing an instruction read out from a program address updated every time when each execution of instruction is completed, includes update ceasing means for ceasing the program address from being updated when an stopping time comes in order to abort a first task defined by a first computer program and overwriting means for overwriting the program address with an initial address of a second computer program when a predetermined time comes in order to start to execute a second task defined by the second computer program at the predetermined time.

Microprocessor starting to execute a computer program at a predetermined interval

It is determined that a write access is executed to a stack area of a main memory. It is then determined whether another write access to a corresponding access destination address in the stack area occurred in the past by referring to an access flag table. In contrast, it is determined that a write access is executed to a global area of the main memory. It is then determined whether another write access to a corresponding access destination address in the global area occurred in the past with referring to an access list. Such a configuration can efficiently provide individual advantages of the determination methods using both the access flag table and the address list. The presence or absence of the past saving execution can be efficiently determined at the time of write access.

Rollback method and information processing apparatus executing the same

A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.

Processor, microcomputer and method for controlling program of microcomputer

Provided is a moving body detecting apparatus capable of detecting only a body to be notified without detecting a body similar in feature to the body to be notified. To confirm whether a break-in body appears in static images from a camera, the apparatus sets a monitoring region for monitoring a window portion in the static images and a monitoring region for monitoring a door body portion therein, and produces difference images from the static images. A pixel set existing in common to the difference images continuing in time sequence is extracted from an image composed so that pixel values reach a maximum. On the basis of the motion vector, a decision is made as to whether the movement of the pixel set from the window portion to the door body portion occurs or not.

Moving body detecting apparatus

A memory control apparatus for controlling the operation of a memory array in a serial memory employs a command control section for registering the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit. Any additional clock signal cycle following shifting of the start bit into the MSB stage of the shift register is detected, so that operating errors caused by noise in the received clock signal can be reliably eliminated.

Memory control apparatus for serial memory

In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.

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Kariya, Japan

Akimasa Niwa