Tensilica, Inc.

Cadence Design Systems, Inc.

Akilesh Parameswar

Ricardo E Gonzalez

Earl A Killian

Dror E Maydan

David W Goodwin

Walter David Lichtenstein

Albert Ren-Rui Wang

Pavlos Konas

Christopher Mark Songer

Rangarajan Srinivasan

Richard Ruddell

Nupur Bhattacharyya

Marines Puig Medina

James Alexander Stuart Fiske

A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Automated processor generation system and method for designing a configurable processor

A processor generation system includes the ability to describe processors with three instruction sizes. In one example implementation, instructions can be 16-, 24- and 64-bits. This enables a new range of architectures that can exploit parallelism in architectures. In particular, this enables the generation of VLIW architectures. According to another aspect, the processor generator allows a designer to add a configurable number of load/store units to the processor. In order to accommodate multiple load/store units, local memories connected to the processor can have multiple read and write ports (one for each load/store unit). This further allows the local memories to be connected in any arbitrary connection topology. Connection box hardware is automatically generated that provides an interface between the load/store units and the local memories based on the configuration.

System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes

Automated processor generation system for designing a configurable processor and method for the same

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San Jose, CA, United States of America

Akilesh Parameswar