Texas Instruments Corporation

Samsung Electronics Co., Ltd.

Other

Lattice Semiconductor Corporation

Akila Subramaniam

Manish Goel

Charles Lance Fuoco

Seok-Jun Lee

Brian Jason Karguth

Hamid Rahim Sheikh

Brian Cruickshank

Denis R Beaudoin

Chunhua Hu

Barry Britton

Samuel Paul Visalli

Michael A Denio

Wai-Bor Leung

David Quintin Bell

Hideo Tamama

Rahul Rithe

Jeffrey Tang

An electronic device, method, and computer readable medium for foveated storage and processing are provided. The electronic device includes a memory, and a processor coupled to the memory. The processor performs head tracking and eye tracking; generates a foveated image from an original image based on the head tracking and the eye tracking; and stores the foveated image using one of: a tile-based method or a frame-based method.

Foveated domain storage and processing

A method of implementing memory transfers for image warping in an electronic device is described. The method comprises receiving an input tile associated with an image; generating a geometric boundary around pixels of the input tile; and remapping the pixels in the geometric boundary to an output tile. An electronic device and a non-transitory computer readable storage medium for performing the method are also disclosed.

Electronic devices for and methods of implementing memory transfers for image warping in an electronic device

A method of enabling processing of a video stream is described. The method comprises establishing a slice width for frames of the video stream; receiving the video stream; dividing, for each frame of the video stream, the frame into vertical slices having the slice width; storing a frame of the video stream in a re-ordered slice based format. Computer-readable storage medium and a device for enabling processing of a video stream are also described.

Device for and method of enabling the processing of a video stream

A low overhead method to handle inter process and peer to peer communication. A queue manager is used to create a list of messages with minimal configuration overhead. A hardware queue can be connected to another software task owned by the same core or a different processor core, or connected to a hardware DMA peripheral. There is no limitation on how many messages can be queued between the producer and consumer cores. The low latency interrupt generation to the processor cores is handled by an accumulator inside the QMSS which can be configured to generate interrupts based on a programmable threshold of descriptors in a queue. The accumulator thus removes the polling overhead from software and boosts performance by doing the descriptor pops and message transfer in the background.

Method for infrastructure messaging

A bus monitoring and debugging system operating independently without impacting the normal operation of the CPU and without adding any overhead to the application being monitored. Users are alerted to timing problems as they occur, and bus statistics that are relevant to providing insight to system operation are automatically captured. Logging of relevant events may be enabled or disabled when a sliding time window expires, or alternatively by external trigger events.

Method and system of debugging multicore bus transaction problems

A method for performing write transactions in an interconnect fabric is described. A burst write transaction is received by a bridge coupled to a master. The burst transaction is initiated by a command phase that includes a wait state attribute. The bridge is also coupled to a second bus that is coupled to a slave destination device or to another bridge. The bridge may initiate a cut-through transaction to the second bus when the wait state attribute indicates a master inserted wait state will not be incurred during the burst transaction.

On-chip interconnect fabric

A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.

Distributed multiple-channel alignment scheme

Growing community of inventors

Dallas, TX, United States of America

Akila Subramaniam