Kabushiki Kaisha Toshiba

Akikuni Sato

Takehiko Hojo

A semiconductor integrated circuit includes a regular cell array, a spare cell array, first and second memory circuits, a determining circuit, a generating circuit and a selecting circuit. When the regular cell array contains a defective regular memory cell, the defective regular memory cell is replaced with a spare memory cell in the spare cell array. Each of the first memory circuits stores data indicating whether an associated spare memory cell is used or not. Any of the second memory circuits stores address data indicating the address of the defective regular memory cell. The determining circuit determines whether each of the spare memory cells is used or not, based on the data stored in an associated first memory circuit. The generating circuit generates predetermined data. The selecting circuit selects and outputs the data generated by the generating circuit or address data stored in each of the second memory circuits.

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Yokohama, Japan

Akikuni Sato