Fujitsu Corporation

Fujitsu Semiconductor Limited

Akiko Satoh

Minoru Saitoh

Takashi Matsuura

Noriko Yabumoto

Zhengjun Zhang

A verification apparatus that verifies whether a reference circuit and an implemented circuit are logically equivalent deletes, respectively therefrom, all buffers and an even number of inverters between flip-flops. On each of the circuits, the apparatus further deletes and merges a flip-flop to another flip-flop that is logically equivalent. The name of the deleted flip-flip is added to the name of the flip-flop to which it is merged. The apparatus compares all of the names of the flip-flops and pairs the flip-flops by name. From the input pin of each of the paired flip-flops, logic cones are defined and using these logic cones, comparison of and verification between the reference circuit and the implemented circuit is performed.

Method and apparatus for logic equivalence verification, and computer product

Data in a data base that describe a logic circuit are converted to a simulation model, and simulations are performed based on them. When it is desired to change a part of the circuit while a simulation is in progress, a tentative correction is made by directly changing the simulation model without entering logics to the data base again. Simulation is continued based on the changed simulation model, then, after the action has been confirmed, the contents of the change are reflected on the data base. In this way, a circuit can easily be changed while simulation is in progress.

Logic simulation system and method

An interactive logic simulation system includes a setting unit for setting at least one display format for logic simulation result information in the form of a window defined by an arbitrary display range by interacting with a user through a display screen; a first management table for managing the display mode of a free-format display format set by the setting unit; a second management table for managing the display mode of a stream display format as a time series display format of the logic simulation result information; a third management table for managing time series data of signal values for each signal terminal constituting the logic simulation result information; and a result display control unit for specifying the logic simulation result information by using management data from the first, second and third management tables, and for displaying the logic simulation result information so specified on the display screen. The system simultaneously displays the logic simulation result information in the free-format display format at a designated time and the logic simulation result information in the stream display format at the designated signal terminal, in the window set on the display screen. Such a construction makes it possible for a user to efficiently conduct execution and analysis of simulation without particularly considering the troublesome procedures and the operations of the logic simulation. When the simulation procedure of the next stage is considered, a high operation factor can be provided by reducing the interruption to the consideration.

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Kawasaki, Japan

Akiko Satoh