Japan Aerospace Exploration Agency

High-reliability Engineering & Components Corporation

Akiko Makihara

Satoshi Kuboyama

Hiroyuki Shindou

Yoshiya Ilde

Akifumi Maru

Tsukasa Ebihara

Yoshiya Iide

Provided are a latch circuit and a flip-flop circuit each having more excellent tolerance to single event upset (SEU). The single event upset (SEU)-tolerant latch circuit of the present invention is configured such that three transistors for redundancy are added to each of eight transistors constituting a conventional DICE latch circuit, at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel, and each of a first data input part and a second data input part is also made dually redundant.

Single event upset-tolerant latch circuit and flip-flop circuit

Disclosed are a latch circuit and a flip-flop circuit, which are capable of suppressing occurrence of a single-event effect, and, in the event of a single-event transient (SET), elimination adverse effects thereof on the circuit. The latch circuit comprises a dual-port inverter, and a dual-port clocked inverter including no transmission gate to reduce a region of strong electric field to be formed. A delay time is set up in a clock to eliminate adverse effects of the SET, and a leading-edge delayed clock to be entered into one of two storage nodes is generated in such a manner as to delay a transition of the storage node and the entire storage nodes from a latch mode to a through mode while preventing an increase in hold time due to the delay time.

Single-event effect tolerant latch circuit and flip-flop circuit

Disclosed is an inverter, a NAND element, a NOR element, a memory element and a data latch circuit which exhibit high tolerance to single event effect (SEE). In an SEE tolerant inverter (I), each of a p-channel MOS transistor and a n-channel MOS transistor which form an inverter is connected in series with an additional second transistor of the same conductive type as that thereof so as to form a double structure (PPNN). Further, a node A between the two p-channel MOS transistors and a node (B) between the two n-channel MOS transistors are connected together through a connection line. Each of an SEE tolerant memory element and an SEE tolerant data latch circuit comprises this SEE tolerant inverter (I).

Single-event-effect tolerant SOI-based inverter, NAND element, NOR element, semiconductor memory device and data latch circuit

Growing community of inventors

Tsukuba, Japan

Akiko Makihara